PTAB

IPR2019-00322

Qualcomm Inc v. Apple Inc

Key Events

Petition

petition

Title: Hardware Automatic Performance State Transitions in System on Processor Sleep and Wake Events
Brief Description: The ’216 patent discloses a system for managing power consumption in an integrated circuit, such as a system-on-a-chip (SOC). The system uses a programmable power management unit (PMU) to transition different "performance domains" between various performance states (e.g., by altering clock frequency or voltage) in response to a processor entering or exiting a sleep state.

Prior Art Relied Upon: Mandelblat (Application # 2007/0043965).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Mandelblat discloses all limitations of the challenged claims. Mandelblat teaches a processor with multiple components, including a processor core and a "Dynamically Sizeable Memory," which constitute a plurality of performance domains. A Power Management Logic (PML) within Mandelblat’s system acts as the claimed PMU, configured to establish performance states for each domain. Specifically, the PML controls the power state (e.g., sleep/wake C-states) of the processor core (the first performance domain) and changes the cache size of the Dynamically Sizeable Memory (the second performance domain). Petitioner contended that changing the memory size is a transition to a "first performance state" that occurs in response to the processor core transitioning to a "second performance state" (e.g., waking from a C4 sleep state to a C0 active state), thus meeting the core limitations of independent claims 1 and 8. Dependent claims were argued to be met by Mandelblat's disclosure of using registers for configuration and transitioning domains between sleep and awake states.

Prior Art Relied Upon: Mandelblat (Application # 2007/0043965) and Kurts (Patent 7,363,523).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner asserted that Mandelblat teaches the foundational system of managing distinct performance domains (a processor core and a sizable memory) based on processor power state. Kurts supplements this by disclosing more granular methods for controlling processor performance states, including specific voltage/frequency pairs stored in a VID table, to manage transitions between sleep and wake states efficiently and reduce latency. The combination, Petitioner argued, renders the claims obvious.
- Motivation to Combine: A person of ordinary skill in the art (POSITA) would have been motivated to combine the references to improve power management. Both Mandelblat and Kurts address the same problem of power management in multi-component processors using ACPI-based C-states. A POSITA would combine Mandelblat’s concept of managing separate component domains with Kurts’s more refined techniques for transitioning processor states to achieve the predictable benefits of improved power savings and reduced latency.
- Expectation of Success: A POSITA would have had a reasonable expectation of success in combining the teachings, as both references operate on well-understood principles of processor power state management and ACPI standards, making their integration straightforward.

Prior Art Relied Upon: Kurts (Patent 7,363,523) and Kang (Patent 7,369,815).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued Kurts teaches a PMU that controls a processor’s transitions between various performance states (C-states) based on voltage and frequency. Kang, in turn, explicitly teaches partitioning a processor into multiple "collapsible" power domains that can be independently powered on or off by a power control unit. Combining these teachings, Kurts provides the mechanism for transitioning a processor (the first performance domain) between sleep and wake states, while Kang provides the concept of other distinct, independently controllable domains (the second performance domain) that would logically have their states adjusted in response.
- Motivation to Combine: Both Kurts and Kang aim to conserve power in portable electronic devices. A POSITA would combine Kang’s architectural approach of partitioning a system into independent power domains with Kurts’s detailed logic for managing processor sleep/wake state transitions. This combination would allow for more granular and efficient power control, achieving greater power savings, a well-known goal in the art.
- Expectation of Success: Combining Kang’s system partitioning with Kurts’s state control logic involves the application of known design principles to achieve the predictable result of enhanced power management.

Petitioner argued that claim terms should be given their broadest reasonable construction. For several key terms, Petitioner requested the Board adopt constructions consistent with those proposed by the Patent Owner (Apple) in parallel district court litigation, ensuring the prior art meets the claims even under the Patent Owner's proposed broader scope.
- "performance domain": Proposed as "one or more components that may be controlled as a unit or independently for performance configuration purposes." This construction supports the argument that components in the prior art that are controlled independently (e.g., a processor core and a memory block) constitute distinct performance domains.
- "power management unit": Argued to be any "hardware and/or software that causes a performance domain to transition to a performance state." This broad construction allows various logic controllers in the prior art, such as the PML in Mandelblat, to qualify as the claimed PMU.
- "establish a . . . performance state": Construed as to "set the one or more performance characteristics to the appropriate values for the performance state," without requiring an actual transition from a different state.

Petitioner requested the institution of an inter partes review and the cancellation of claims 1–3, 6, 8–10, and 13 of the ’216 patent as unpatentable.