PTAB

IPR2019-00861

Samsung Electronics Co Ltd v. NuCurrent Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Multi-layer-multi-turn structure for high efficiency inductors
  • Brief Description: The ’046 patent describes a high-efficiency inductor for use in electric circuits, particularly those in the radio frequency range. The invention focuses on a multi-layer, multi-turn structure comprising multiple conductor layers separated by insulator layers, configured to reduce resistance loss.

3. Grounds for Unpatentability

Ground 1: Obviousness over Partovi and Chiang - Claims 1-3, 10, 15-21, 23-26, 28, and 29 are obvious over Partovi in view of Chiang.

  • Prior Art Relied Upon: Partovi (Application # 2009/0096413) and Chiang (Patent 7,248,138).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Partovi disclosed a method of manufacturing an inductor for an inductive power transfer system using a multi-layer printed circuit board (PCB) coil. This coil, created from separate, stacked PCB layers (e.g., layers 357 in Fig. 18), met the limitations of providing first and second electrically conductive conductor layers separated by an insulator layer. While Partovi disclosed connecting these layers with a via or contact, it did not explicitly teach a parallel connection using at least two connectors. Chiang was argued to supply this missing element, as it explicitly taught connecting conductive layers in a multi-layer PCB inductor "in parallel to decrease the impedance of a particular turn" using multiple plated through-holes (vias), which function as connectors. The combination therefore allegedly rendered the method of independent claim 1 obvious. Dependent claims were argued to be obvious as they recited inherent properties of inductors (claims 2-3), obvious design choices based on Partovi's disclosure of copper layers (claims 10, 15, 25), or features explicitly taught by the combination (claims 16-19, 23-24, 28-29).
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine these references to solve a known problem. Partovi acknowledged that stacking coil layers in series increases resistance and power loss. A POSITA seeking to improve the efficiency of Partovi’s multi-layer inductor—a stated goal of Partovi—would have looked to known techniques for reducing resistance in PCB inductors, such as the parallel connection method taught by Chiang.
    • Expectation of Success: A POSITA would have had a reasonable expectation of success because combining Chiang's method of using parallel vias with Partovi's PCB-based inductor involved applying known PCB fabrication techniques to similar structures to achieve the predictable result of reduced resistance and improved efficiency.

Ground 2: Obviousness over Partovi, Chiang, and Tseng - Claims 6, 7, and 13 are obvious over the combination of Partovi, Chiang, and Tseng.

  • Prior Art Relied Upon: Partovi (Application # 2009/0096413), Chiang (Patent 7,248,138), and Tseng (Patent 9,912,173).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon the Partovi and Chiang combination by adding Tseng to address specific dimensional and performance characteristics. For claims 6 and 7, which required conductor layer thicknesses of about 1.25 to 4 times the skin depth, Petitioner asserted that Tseng explicitly taught making the metal thickness "more than twice of the skin depth" to reduce power loss. For claim 13, which required an inductor quality factor (Q factor) greater than 5, Tseng taught that optimizing the spacing between conductive traces improves the Q factor from 50 to 100.
    • Motivation to Combine: A POSITA building the inductor of Partovi/Chiang would have been motivated to consult a reference like Tseng to optimize its performance. Reducing conductor loss due to skin effect and improving the Q factor are well-known objectives in inductor design. Tseng provided explicit, predictable solutions for these very issues in the context of coil inductors for wireless power transfer.

Ground 3: Obviousness over Partovi, Chiang, and Phan - Claims 8, 12, 26, and 27 are obvious over the combination of Partovi, Chiang, and Phan.

  • Prior Art Relied Upon: Partovi (Application # 2009/0096413), Chiang (Patent 7,248,138), and Phan (Patent 7,601,919).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground added Phan to the primary combination to address further physical characteristics of the inductor layers. For claim 8's requirement that the first and second conductor layers have "about the same" thickness, Phan was cited as disclosing a multi-layer PCB where each conductor layer has the same thickness (0.0007 inches). For claim 12, requiring an insulating layer thickness of less than 5 cm, Phan disclosed insulating layers of Kapton with a thickness of 0.003 inches, which is substantially less than 5 cm. Phan’s disclosure of using Kapton, a well-known non-conductive dielectric material, was also used to map to the limitations of claims 26 and 27.
    • Motivation to Combine: Petitioner argued that making conductor layers the same thickness was one of a finite number of simple design choices. Furthermore, a POSITA motivated by Partovi’s goal of creating a "compact" and "lightweight" device would seek to minimize the inductor's total thickness. Phan provided a known method for achieving this by using very thin, commercially available insulating materials like Kapton in a multi-layer PCB stackup.

  • Additional Grounds: Petitioner asserted an additional obviousness challenge against claim 5 based on the combination of Partovi, Chiang, and Hu (an IEEE publication from July 2001), relying on Hu's teaching that a conductor thickness of one to two skin depths is sufficient for near-minimum AC resistance.

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-3, 5-8, 10, 12-13, 15-21, and 23-29 of the '046 patent as unpatentable.