Lenovo Holding Co Inc v. PhoTonic Imaging Solutions Inc

1. Case Identification

• Case #: IPR2019-01075
• Patent #: 7,113,203
• Filed: May 9, 2019
• Petitioner(s): Lenovo Holding Company, Inc.; Lenovo (United States) Inc.
• Patent Owner(s): Photonic Imaging Solutions, Inc.
• Challenged Claims: 1-38

2. Patent Overview

• Title: Method and System for Single-Chip Camera
• Brief Description: The ’203 patent describes digital cameras that integrate an image sensor, analog-to-digital converter, data storage, and input/output interface controllers onto a single semiconductor chip to create a low-cost, low-power system.

3. Grounds for Unpatentability

Ground 1: Claims 1-15, 17-20, 22-32, and 33-38 are obvious over [Rockoff](https://ai-lab.exparte.com/case/ptab/IPR2019-01075/doc/1004), [Smith](https://ai-lab.exparte.com/case/ptab/IPR2019-01075/doc/1005), and [Kwon](https://ai-lab.exparte.com/case/ptab/IPR2019-01075/doc/1006).

• Prior Art Relied Upon: Rockoff (WO 00/36562), Smith (an IEEE Journal article from Dec. 1998), and Kwon (Patent 6,633,335).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Rockoff taught the general architecture of a digital camera system, including a processor, memory, and communication interfaces on a single chip, but disclosed the image sensor as a separate component. Smith taught that semiconductor technology had advanced sufficiently to fabricate all camera components, including the image sensor and processing logic, on a single chip. Kwon taught using an on-chip multiplexer to allow an I/O pin to selectively connect to either a register for controlling external functions or to internal circuitry for testing purposes, thereby adding test functionality without requiring additional pins. The combination of these references allegedly disclosed every element of independent claims 1 and 27.
  • Motivation to Combine: A POSITA would combine Rockoff and Smith because Rockoff expressly suggested integrating the image sensor onto the same chip as the processing apparatus to reduce manufacturing costs, decrease size, and lower power consumption, and Smith demonstrated the feasibility of such a single-chip design. A POSITA would further incorporate Kwon’s teachings to add a test function to the Rockoff system to verify internal circuitry, a known benefit. Using Kwon's multiplexer approach was motivated by the desire to add this functionality efficiently without the cost and complexity of adding dedicated test pins, instead repurposing existing general-purpose I/O (GPIO) pins.
  • Expectation of Success: Petitioner asserted there was a high expectation of success, as the combination involved integrating well-known, predictable components (single-chip cameras, multiplexers, testing circuits) using established design principles to achieve recognized benefits.

Ground 2: Claims 16 and 32 are obvious over Rockoff, Smith, and Kwon in view of [Chevallier](https://ai-lab.exparte.com/case/ptab/IPR2019-01075/doc/1007).

• Prior Art Relied Upon: Rockoff (WO 00/36562), Smith (an IEEE Journal article from Dec. 1998), Kwon (Patent 6,633,335), and Chevallier (Patent 6,879,340).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground built upon the combination in Ground 1, adding Chevallier to address the limitation of a non-volatile memory data storage element (claim 16) and wavelet compression (claim 32). Petitioner asserted that Chevallier taught an integrated CMOS image sensor and DSP that used non-volatile storage for image data, preventing data loss if power was removed. Chevallier also confirmed that wavelet coding was a well-known compression technique.
  • Motivation to Combine: A POSITA would have been motivated to add a common component like non-volatile memory, as taught by Chevallier, to the single-chip camera system of Rockoff/Smith/Kwon to provide the known benefit of preserving stored image data during power loss. Similarly, incorporating wavelet compression was presented as an obvious design choice to provide users with another well-known compression option.
  • Expectation of Success: Adding a standard memory type and a known compression algorithm to a camera system were routine modifications for a POSITA.

Ground 3: Claims 6-8 and 21 are obvious over Rockoff, Smith, and Kwon in view of [Roustaei](https://ai-lab.exparte.com/case/ptab/IPR2019-01075/doc/1009).

• Prior Art Relied Upon: Rockoff (WO 00/36562), Smith (an IEEE Journal article from Dec. 1998), Kwon (Patent 6,633,335), and Roustaei (Application # 2002/0050518).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground added Roustaei to the primary combination to address limitations related to specific A/D converter bit-depths (8-bit, 10-bit, and 12-bit in claims 6-8) and a power-monitoring block (claim 21). Roustaei taught using 8-bit, 10-bit, and 12-bit A/D converters with CMOS imagers to improve image quality and also disclosed a low-power shutdown mode.
  • Motivation to Combine: Petitioner argued a POSITA would combine Roustaei’s teachings as it was a simple design choice to select A/D converters with different bit depths to balance image quality against cost and complexity. A POSITA would also be motivated to add a power-monitoring and shutdown circuit, as taught by Roustaei, to the camera system to conserve battery life, a critical consideration for portable electronic devices.
• Additional Grounds: Petitioner asserted an additional obviousness challenge (Ground 4) for claims 34-37 based on the combination of Rockoff, Smith, and Kwon in view of Silverbrook (WO 01/02905). This ground argued it would have been obvious to implement various well-known communication interfaces (USB, IEEE 1394, LAN, Bluetooth) as taught by Silverbrook.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under §325(d) would be inappropriate. It contended that the grounds presented were not the same or substantially the same as those considered during prosecution because the petition relied on prior art references, particularly Smith and Kwon, that were not of record or considered by the Examiner. These new references were alleged to teach the very limitations that led to the allowance of the claims.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-38 of the ’203 patent as unpatentable.