Intel Corp v. VLSI

1. Case Identification

• Case #: IPR2019-01199
• Patent #: 7,247,552
• Filed: June 25, 2019
• Petitioner(s): Intel Corporation
• Patent Owner(s): VLSI Technology LLC
• Challenged Claims: 20

2. Patent Overview

• Title: Method of Making an Integrated Circuit Having a Plurality of Bond Pads
• Brief Description: The ’552 patent describes a method for manufacturing integrated circuits (ICs) that addresses mechanical stress on bond pads during external connection. The purported invention involves modifying the IC layout to add "dummy metal lines" in the interconnect layers beneath the bond pads to increase the metal density, thereby improving structural integrity.

3. Grounds for Unpatentability

Ground 1: Claim 20 is obvious over Kanaoka, Weling, and Reddy.

• Prior Art Relied Upon: Kanaoka (Patent 7,102,223), Weling (Patent 5,639,697), and Reddy (a 2001 M.S. Thesis titled "Digital Design Flow Options").
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that the claimed method is a straightforward combination of well-known concepts. Reddy disclosed the standard, multi-step "design flow" for creating an IC: (1) developing a circuit design, (2) developing a corresponding layout, (3) modifying the layout to comply with design rules, and (4) fabricating the IC. Kanaoka taught adding dummy metal lines below bond pads to make the metal density uniform (preferably 50% or more) across interconnect layers, solving the same structural problem addressed by the ’552 patent. Weling independently taught adding dummy lines to "commonize" pattern density across different layers of an IC, specifically teaching a target density of approximately 40%-80% of the entire surface area. Petitioner contended that applying the specific density targets from Kanaoka and Weling within the standard design process taught by Reddy renders all steps of claim 20 obvious.
  • Motivation to Combine: A person of ordinary skill in the art (POSITA) would naturally use a standard design flow like Reddy's to implement the IC structures of Kanaoka and Weling. All three references are in the same field of IC design and address related manufacturing challenges. A POSITA, seeking to improve structural uniformity as taught by Kanaoka, would have been motivated to implement Weling’s specific teaching of a 40% minimum metal density to achieve predictable, robust results. Using Reddy’s computer-aided design (CAD) tools and iterative design rule checks (DRC) to implement these density requirements was described as a standard, efficiency-driven practice.
  • Expectation of Success: Petitioner asserted that a POSITA would have had a high expectation of success, as the combination involved applying known techniques (Reddy's design flow, Weling's density rules) to solve a known problem (non-uniformity under bond pads, as identified by Kanaoka) to achieve a predictable outcome.

Ground 2: Claim 20 is obvious over Kanaoka, Weling, and Vuong.

• Prior Art Relied Upon: Kanaoka (Patent 7,102,223), Weling (Patent 5,639,697), and Vuong (Application # US 2004/0098674).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground is similar to Ground 1 but substitutes Vuong for Reddy as the source for the IC design process. Vuong, like Reddy, taught a standard process for designing and manufacturing an IC. Critically, Vuong’s disclosed "Layout/Place&Route Tool" explicitly included a "Metal Fill" step in its automated design flow. This step was described as a common approach to increase metal density and improve planarity. Petitioner argued that Vuong provides an even more explicit roadmap for modifying a layout by adding dummy metal. The structural teachings of Kanaoka (dummy lines under bond pads) and Weling (40% minimum density) map to this combination in the same manner as in Ground 1.
  • Motivation to Combine: The motivation was analogous to Ground 1. A POSA would combine the known design goal from Kanaoka and Weling (uniform, high-density metal layers) with a standard, commercially-relevant design tool and process from Vuong that already contemplated adding metal fill. Vuong originated from Cadence Design Systems, a leading manufacturer of layout tools, making its teachings particularly relevant to a POSITA. The combination was presented as the application of a known solution (metal fill) to achieve a known benefit (uniformity and planarity).
  • Expectation of Success: As with Ground 1, Petitioner argued success would be predictable. Combining the specific structural improvements from Kanaoka and Weling using an established design methodology from Vuong that explicitly includes a metal fill step would have been a straightforward implementation of known engineering principles.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under §314(a) and §325(d) would be inappropriate. The petition was filed in parallel with district court litigation (VLSI Technology LLC. v. Intel Corporation, No. 18-966-CFC (D. Del.)). Petitioner asserted that the IPR should proceed because the specific prior art combinations and arguments were not before the Patent Office during prosecution. Furthermore, Petitioner contended that the complexity and breadth of the district court case, which involved numerous patents, would limit its ability to fully present these invalidity defenses at trial.

5. Relief Requested

• Petitioner requested the institution of an inter partes review and cancellation of claim 20 of Patent 7,247,552 as unpatentable under 35 U.S.C. §103.