PTAB

IPR2019-01200

Intel Corp v. VLSI Technology LLC

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Method of Making an Integrated Circuit
  • Brief Description: The ’552 patent describes a method for manufacturing integrated circuits (ICs) to address mechanical stress and potential damage under bond pads during fabrication. The purported invention involves defining a "force region" under the bond pad and adding "dummy" metal structures in the underlying interconnect layers to increase metal density and provide structural reinforcement.

3. Grounds for Unpatentability

Ground 1: Claim 11 is obvious over Oda in combination with Cwynar and Reddy.

  • Prior Art Relied Upon: Oda (Application # 2004/0150112), Cwynar (Application # 2002/0162082), and Reddy (a 2001 M.S. Thesis).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that the method of claim 11 is a straightforward application of known IC design and manufacturing techniques. Oda was asserted to teach the core concept of adding "dummy" metal patterns in multiple interconnect layers below a bond pad to function as shock-resistant layers, addressing the same stress problem as the ’552 patent. Cwynar was presented to teach a process for adding "dummy fill" features (explicitly including "dummy metal lines") into layout regions to achieve a desired, uniform metal density for planarity. Reddy was cited for disclosing the well-known, standard "design flow" for creating an IC, which involves the claimed steps of developing a circuit design, developing a corresponding layout using automated tools, and modifying that layout based on design rule checks (DRCs).
    • Motivation to Combine: A POSITA would combine these references as they are all in the same field of endeavor: IC design and fabrication. Petitioner asserted a POSITA implementing Oda’s method for stress reduction would naturally use the standard design flow taught by Reddy. When needing to control metal density for planarity and shock resistance—problems addressed by both Oda and Cwynar—a POSITA would have looked to Cwynar’s specific method of adding dummy lines to achieve a target density. The combination was presented as an application of known techniques to solve known problems.
    • Expectation of Success: A POSITA would have had a high expectation of success because combining the references involved applying established CAD tools and design methodologies (Reddy) to implement known solutions (Oda’s dummy patterns and Cwynar’s dummy lines) for predictable results, namely improved planarity and structural integrity.

Ground 2: Claim 11 is obvious over Oda in combination with Owada and Vuong.

  • Prior Art Relied Upon: Oda (Application # 2004/0150112), Owada (Patent 5,027,188), and Vuong (Application # 2004/0098674).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground presented an alternative combination to show obviousness. Oda was again used as the primary reference teaching dummy patterns under a bond pad. Owada was asserted to also teach adding dummy metal lines below a solder bump to increase wiring density, thereby creating a flatter, more reliable surface for the overlying bond pad. Vuong was argued to teach a modern, automated IC design flow that explicitly integrates a "metal fill" step to modify a layout. Vuong’s tool automatically adds metal fill to meet density requirements as part of an iterative layout, verification, and modification process, directly corresponding to the steps of the challenged claim.
    • Motivation to Combine: Petitioner argued a POSITA would combine Oda and Owada as they both address related problems in IC fabrication (stress, planarity, defects) using the same solution (adding dummy metal under bonding structures). To implement this, a POSITA would be motivated to use an automated design tool like that taught by Vuong, which was designed specifically to handle such layout modifications through its integrated metal-fill process. Using Vuong’s process to implement the teachings of Oda and Owada was framed as a common-sense application of a tool to a task it was designed for.
    • Expectation of Success: A POSITA would have expected success because Vuong’s automated process was a common approach for managing metal density. Applying this established, predictable process to implement the dummy line structures of Oda and Owada would have been a routine design choice.

4. Key Claim Construction Positions

  • Petitioner argued that the term "force region" should be construed according to its express definition in the ’552 patent’s specification: "a region within the integrated circuit in which forces are exerted on the interconnect structure when a die attach is performed."
  • Petitioner contended that this construction is controlling due to lexicography. It further argued against Patent Owner's asserted construction in district court ("an area in which a defect may occur due to a contact made to the bond pad"). Petitioner asserted the Patent Owner's construction was improperly broad and would render other claim limitations, such as the requirement for the region to be "susceptible to defects," redundant and meaningless.

5. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under §314(a) and §325(d) would be inappropriate. The petition asserted that:
    • The prior art and invalidity arguments presented in the IPR had not been previously considered by the USPTO.
    • There was significant uncertainty as to whether a trial in the parallel district court litigation would conclude before a Final Written Decision in the IPR.
    • The invalidity defense presented in the IPR (specifically Ground 2) could not be pursued in the district court due to court-ordered narrowing of defenses, making the IPR an effective and efficient alternative for resolving these unique issues.

6. Relief Requested

  • Petitioner requested the institution of an inter partes review and the cancellation of claim 11 of Patent 7,247,552 as unpatentable under 35 U.S.C. §103.