PTAB

IPR2019-01262

Intel Corp v. Tela Innovations Inc

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Semiconductor Integrated Circuit Device with Regular Layout
  • Brief Description: The ’352 patent discloses a "dynamic array" architecture for semiconductor integrated circuits intended to improve manufacturing yields. The invention is characterized by a restricted, regular layout style where features in layers above the substrate, such as gate electrodes and interconnects, are required to be "linear-shaped features" extending in a single common direction.

3. Grounds for Unpatentability

Ground 1: Obviousness over IBM Chang and Kitabayashi - Claims 1, 16, 17, and 19 are obvious over IBM Chang in view of Kitabayashi.

  • Prior Art Relied Upon: IBM Chang (Patent 7,465,973) and Kitabayashi (Patent 7,200,831).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that the combination of IBM Chang and Kitabayashi disclosed all limitations of the challenged claims. IBM Chang was asserted to teach the front-end aspects of the claims, specifically a semiconductor layout for SRAM cells with a "completely periodic grating" of gates and active regions. This included regularly spaced, parallel, linear gate electrode tracks formed by a "line and cut" process to improve manufacturability and packing density, satisfying the limitations of independent claim 1 related to the substrate and gate layers. To address the back-end interconnect limitations, Petitioner turned to Kitabayashi, which taught a multilayer interconnect system also focused on improving yield by using regular wiring patterns. Kitabayashi explicitly disclosed using the same "line and cut" technique to create interconnect layers where each layer contains parallel, strip-like wiring traces extending in a single common direction. Petitioner contended this directly taught the interconnect limitations of claim 1.
    • For the dependent claims, Petitioner argued IBM Chang’s disclosure of repeated SRAM cells, which inherently contain different diffusion region sizes (larger n-type vs. smaller p-type regions), rendered claim 16 obvious. Petitioner further asserted that IBM Chang’s depiction of gate electrode contacts that are rectangular and larger than the underlying gate line to simultaneously contact gate and active regions met the limitations of claims 17 and 19.
    • Motivation to Combine (for §103 grounds): Petitioner presented three primary motivations for a Person of Ordinary Skill in the Art (POSITA) to combine the references. First, the references were complementary: IBM Chang focused on the front-end (gate layer) and explicitly stated that back-end interconnection "is thus not a primary focus," suggesting many methods were available. Kitabayashi provided a simple, versatile, and well-known back-end (interconnect) solution that improved reliability and yield. A POSITA would have been motivated to apply Kitabayashi’s proven back-end technique to IBM Chang’s front-end design to achieve end-to-end manufacturability benefits. Second, both references taught the same "line and cut" layout technique for the same purpose—improving manufacturability—albeit in different device layers. A POSITA would have found it obvious to apply this consistent methodology across the entire device.
    • Expectation of Success (for §103 grounds): Petitioner argued a POSITA would have had a high expectation of success, as the combination involved applying a known, simple layout technique from Kitabayashi to a compatible front-end structure from IBM Chang to achieve the predictable benefit of improved overall device yield and performance.

4. Key Claim Construction Positions

  • Petitioner argued that several claim terms required construction but focused on the term "linear gate electrode segment / linear conductor segment."
    • Petitioner proposed construing "linear" as "having a consistent vertical cross-section shape and extending in a single direction over the substrate."
    • This proposed construction was not based on the plain and ordinary meaning alone but was taken directly from the specification of the ’352 patent. Petitioner highlighted that the patent expressly defined ("characterized") a "linear-shaped layout feature" in this manner. This definition was asserted to be a core aspect of the purported invention, and its application was critical to demonstrating how the prior art, which disclosed structures with these exact characteristics, rendered the claims obvious.

5. Relief Requested

  • Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 1, 16, 17, and 19 of the ’352 patent as unpatentable under 35 U.S.C. §103.