Intel Corp v. VLSI Technology LLC

1. Case Identification

• Case #: IPR2020-00106
• Patent #: 7,725,759
• Filed: October 31, 2019
• Petitioner(s): Intel Corporation
• Patent Owner(s): VLSI Technology LLC
• Challenged Claims: 1-4, 7-8, 13-15, and 17

2. Patent Overview

• Title: Method and Apparatus for Selectively Altering a Clock Frequency in an Electronic Device
• Brief Description: The ’759 patent describes a method for managing power consumption in an electronic device by selectively adjusting clock frequency. The system involves multiple "master devices" on a bus, where a first master device requests a change to a high-speed clock in response to a measured change in its performance, and a clock controller then provides the adjusted clock frequency to a second master device and the bus.

3. Grounds for Unpatentability

Ground I: Claims 1-2, 4, 7-8, 13-14, and 17 are obvious over Shaffer in view of Lint.

• Prior Art Relied Upon: Shaffer (Patent 6,298,448) and Lint (Patent 7,360,103).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Shaffer disclosed the core elements of independent claims 1 and 14. Shaffer teaches a system with multiple master devices (CPU, controllers) coupled to a bus, where a CPU (first master device) requests clock frequency changes from a programmable clock module based on dynamically monitored CPU utilization. This utilization monitoring constitutes a "predefined change in performance." Shaffer further teaches that its clock module provides the variable clock signal to other controllers (second master devices) and the system bus, thereby controlling their clock frequencies.
  • Motivation to Combine: While Shaffer taught adjusting clock speed based on CPU utilization, it did not specify how to measure it over time. Petitioner asserted Lint remedied this by teaching the measurement of average processor performance over a "predetermined interval" to determine the appropriate clock speed for power savings. A POSITA would combine Lint's well-known performance measurement technique with Shaffer’s similar system to achieve the predictable result of improved power management by making Shaffer's utilization monitoring more precise.
  • Expectation of Success: A POSITA would have had a high expectation of success as the combination involved applying a known monitoring technique (from Lint) to an existing system (Shaffer) to improve a known parameter (power efficiency).

Ground II: Claim 3 is obvious over Shaffer in view of Lint and Taketoshi.

• Prior Art Relied Upon: Shaffer (Patent 6,298,448), Lint (Patent 7,360,103), and Taketoshi (Application # 2005/0102560).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground builds on Ground I and specifically addresses the limitation of claim 3, which requires that a "clock-frequency evaluation results in setting a high-speed clock flag." Petitioner contended that Taketoshi explicitly taught this element, describing a "clock frequency determining section" that evaluates performance requirements and a "flag adding section" that sets "clock control flags" in instruction code to manage clock speeds in a multi-processor system.
  • Motivation to Combine: Petitioner argued a POSITA would be motivated to incorporate Taketoshi's clock flag mechanism into the Shaffer/Lint system. Since Shaffer, Lint, and Taketoshi all address the problem of adjusting clock frequency in multi-device systems to balance performance and power consumption, using Taketoshi's flags would be a known, suitable method to implement the clock speed changes determined by the Shaffer/Lint system, enabling better processing maintenance and power reduction.

Ground III: Claims 1-4, 7-8, 13-15, and 17 are obvious over Chen in view of Terrell.

• Prior Art Relied Upon: Chen (Patent 5,838,995) and Terrell (Application # 2004/0098631).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued Chen taught a system with multiple master devices on a bus that request a higher clock frequency (e.g., 100MHz vs. a 50MHz default) when a transaction requires it. This request, based on determining a "particular transaction" where "higher frequency operation is desired," meets the "predefined change in performance" limitation. Chen's clock logic then provides the higher clock frequency to both the requesting device, other devices, and the bus.
  • Motivation to Combine: Chen's system adjusts frequency based on the capability of the devices for a transaction, not the actual, real-time need. Terrell was introduced as teaching a method to save power by adjusting a shared clock based on the measured, real-time workload of multiple processors over a "sample period." Petitioner argued a POSITA would combine Terrell's need-based workload measurement with Chen's capability-based system to optimize power consumption by ensuring the clock speed was increased only when necessary, not just because a device was capable of higher speeds. Terrell itself stated its features were "desirable" for on-chip bus systems like Chen's, providing an explicit motivation.
  • Expectation of Success: Combining the known technique of workload measurement from Terrell with the bus arbitration system of Chen would predictably result in a more power-efficient system, representing a routine design choice for a POSITA.

4. Arguments Regarding Discretionary Denial

• Petitioner argued against discretionary denial under 35 U.S.C. §314(a) and §325(d). It contended that the petition should be granted because the invalidity arguments presented had not been previously considered by the USPTO and that an inter partes review (IPR) would be an efficient alternative to addressing these unique validity issues in parallel district court litigation.

5. Relief Requested

• Petitioner requested institution of an IPR and cancellation of claims 1-4, 7-8, 13-15, and 17 of the ’759 patent as unpatentable.