Intel Corp v. VLSI Technology LLC

1. Case Identification

• Case #: IPR2020-00142
• Patent #: 6,633,187
• Filed: November 22, 2019
• Petitioner(s): Intel Corporation
• Patent Owner(s): VLSI Technology LLC
• Challenged Claims: 13, 17, and 18

2. Patent Overview

• Title: Power on Reset Techniques for an Integrated Circuit Chip
• Brief Description: The ’187 patent discloses a power-on-reset (POR) technique for an integrated circuit (IC) that includes an on-chip power converter. The claimed invention involves establishing a reset condition, receiving a power enable signal to activate the on-chip converter, and then enabling the IC’s functionality only after the generated power supply has stabilized.

3. Grounds for Unpatentability

Ground I: Obviousness of Claims 13 and 17 over Page, Yamamoto, and Stratakos

• Prior Art Relied Upon: Page (Patent 6,980,037), Yamamoto (Patent 5,778,237), and Stratakos (High-Efficiency Low-Voltage DC-DC Conversion for Portable Applications, Ph.D. Thesis).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Page disclosed a stand-alone IC with an on-chip switched power converter and a POR circuit that establishes an idle state until voltage is stable, fulfilling most limitations of claim 13. Petitioner contended that while Page teaches implementing its POR functionality in software via "control instructions," it does not explicitly disclose the requisite processing module and memory. Yamamoto was introduced to supply this teaching, as it discloses a single-chip microcomputer with a CPU, RAM/ROM, and POR functionality. For claim 17, which adds generating a clock signal and power converter regulation signals, Petitioner argued Page's phase-locked loop (PLL) generates the necessary clock signal. Stratakos was then combined to teach using such a clock signal to generate the power converter regulation signals, a detail not explicit in Page.
  • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine Page with Yamamoto to implement the software-based POR functions described in Page, as integrating a processor and memory is a well-known, advantageous method for executing software on an IC. A POSITA would look to Stratakos because Page expressly references a conference paper by Stratakos on the subject of switching converters, directly motivating a skilled artisan to consult Stratakos's work for implementation details, such as using a system clock to control the converter.
  • Expectation of Success: A POSITA would have a high expectation of success, as combining a standard processor and memory to execute software instructions was a routine and predictable design choice. Similarly, using a clock signal to drive a switching converter, as taught by Stratakos, was a conventional technique.

Ground II: Obviousness of Claim 18 over Page, Yamamoto, Stratakos, and Bujanos

• Prior Art Relied Upon: Page (Patent 6,980,037), Yamamoto (Patent 5,778,237), Stratakos (Ph.D. Thesis), and Bujanos (Patent 5,949,227).

• Core Argument for this Ground:

  • Prior Art Mapping: This ground builds upon the combination for claim 17. Dependent claim 18 adds the limitation that the processing module enables the power converter by "enabling a band-gap reference that is used in generating the power converter regulation signals." Petitioner argued that Stratakos teaches that switching regulators commonly use a reference voltage for regulation and that band-gap references are often required for their stability. However, Stratakos does not explicitly teach enabling the band-gap reference in response to a power enable signal. Bujanos was introduced to supply this missing element, as it discloses a band-gap reference circuit that receives an "enable signal" to control its operation and save power.
  • Motivation to Combine: A POSITA, implementing the switching regulator in Page according to the teachings of Stratakos, would be motivated to use a band-gap reference for its known temperature stability benefits. A POSITA would further be motivated to incorporate the teachings of Bujanos to add an enable feature to this band-gap reference. This is because power saving is a primary goal in IC design, and Page itself is directed to a low-power IC. Enabling the reference only when needed is a known technique to achieve such power savings.
  • Expectation of Success: Combining these elements would have been predictable. Using band-gap references in regulators was a well-established practice, and adding an enable signal for power management, as taught by Bujanos, was a straightforward and conventional design modification.

• Additional Grounds: Petitioner asserted additional obviousness challenges based on Yasuda (Patent 5,936,443) as the primary reference, combined with Page, Yamamoto, Stratakos, and Bujanos in various permutations to challenge claims 13, 17, and 18. These grounds relied on similar rationales, substituting Yasuda’s disclosure of an IC with a POR circuit and an internal voltage generator for the primary teachings of Page.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that the Board should not exercise discretionary denial under 35 U.S.C. §314(a) despite a parallel district court case. Petitioner asserted that an inter partes review (IPR) is a more efficient and expert forum for adjudicating the complex, multi-reference obviousness challenges presented. It was also argued that the trial date in the co-pending litigation was uncertain, and that an IPR could reach a Final Written Decision (FWD) before a final, appealable judgment from the district court. Petitioner further contended it was diligent in filing the petition.

5. Relief Requested

• Petitioner requested institution of an IPR and cancellation of claims 13, 17, and 18 of the ’187 patent as unpatentable.