Intel Corp v. VLSI Technology LLC

1. Case Identification

• Case #: IPR2020-00158
• Patent #: 7,523,373
• Filed: November 20, 2019
• Petitioner(s): Intel Corporation
• Patent Owner(s): VLSI Technology LLC
• Challenged Claims: 1-13, 15-16

2. Patent Overview

• Title: Minimum Memory Operating Voltage Technique
• Brief Description: The ’373 patent discloses a method for managing power in an integrated circuit containing a processor and memory. The alleged invention involves determining and storing the memory's minimum operating voltage and using a power supply selector to ensure the voltage supplied to the memory does not drop below this stored minimum, even when the processor's voltage is lowered to conserve power.

3. Grounds for Unpatentability

Ground 1: Claims 1-7, 9-11, 13, and 15-16 are obvious over Harris, Abadeer, and Zhang.

• Prior Art Relied Upon: Harris (Patent 5,867,719), Abadeer (Application # 2006/0259840), and Zhang (Application # 2003/0122429).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Harris taught the core system of an integrated circuit with a processor (CPU) and memory, including a voltage switching circuit to provide one of two voltages (VDD or VSTBY) to the memory. Harris disclosed switching to the VSTBY voltage to prevent data loss if the primary VDD voltage dropped below a threshold, or as part of a low-power mode where the CPU voltage is lowered. Petitioner contended that Abadeer supplied the missing step of determining and storing a memory's minimum operating voltage using a Built-In-Self-Test (BIST) and storing the value in non-volatile memory (fuses). Finally, Zhang was cited for its teaching of using on-chip integrated voltage regulators to provide stable, adjustable supply voltages to different components, such as a processor, which would render the "regulated voltage" limitations of the claims obvious.
  • Motivation to Combine: A POSITA would combine Harris with Abadeer to implement Harris's voltage threshold feature. While Harris taught switching voltages based on a "set level or threshold," it did not specify how to determine that threshold. Abadeer provided a well-known method for determining a component's minimum operating voltage, which a POSITA would have naturally used to implement the system in Harris predictably and reliably. A POSITA would incorporate Zhang's integrated regulators into the Harris system to provide stable and independently controllable voltages, a known technique for improving performance and managing power consumption.
  • Expectation of Success: The combination involved applying known techniques (Abadeer's voltage determination, Zhang's regulators) to a conventional system (Harris's circuit) to achieve predictable results, such as improved power management and reliable data retention.

Ground 2: Claims 2 and 11-12 are obvious over Harris, Abadeer, Zhang, and Cornwell.

• Prior Art Relied Upon: Harris (Patent 5,867,719), Abadeer (Application # 2006/0259840), Zhang (Application # 2003/0122429), and Cornwell (Patent 7,702,935).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground built upon the combination in Ground 1. It addressed dependent claims requiring the minimum operating voltage to be one of a minimum write voltage, minimum read voltage, or minimum standby voltage. While Abadeer taught testing for a minimum standby voltage, Petitioner argued that Cornwell explicitly taught determining and recording minimum read and write operating voltages for a memory during the manufacturing process to optimize power consumption.
  • Motivation to Combine: A POSITA seeking to optimize the power-saving features of the Harris/Abadeer/Zhang system would have been motivated to test for the minimum operating voltages for different memory functions (read, write, standby), as taught by Cornwell. Lowering the voltage to the specific minimum required for a given operation was a known method for maximizing power savings. A POSITA would combine Cornwell’s teachings to make the base system more efficient and functionally granular.
  • Expectation of Success: A POSITA would have a reasonable expectation of success in applying Cornwell's specific voltage testing methods to the combined system, as it represented a further, predictable optimization of a known power-saving strategy.

Ground 3: Claim 8 is obvious over Harris, Abadeer, Zhang, and Bilak.

• Prior Art Relied Upon: Harris (Patent 5,867,719), Abadeer (Application # 2006/0259840), Zhang (Application # 2003/0122429), and Bilak (Application # 2005/0188230).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground also built upon the combination in Ground 1, but specifically addressed claim 8, which required the step of determining the minimum voltage to be performed by a test "applied externally from the integrated circuit." While Abadeer taught an internal BIST, Petitioner asserted that Bilak explicitly disclosed determining the minimum operating voltage of an integrated circuit "during testing of the IC (typically by an external tester during manufacturing test)."
  • Motivation to Combine: A POSITA would have recognized that determining minimum operating voltage could be done either internally (as in Abadeer) or externally (as in Bilak). Bilak taught that using external testers was a "well known" technique. A POSITA would have found it obvious to use an external tester as taught by Bilak to implement the voltage determination step for the Harris/Zhang system, as it was one of a finite number of predictable design choices.
  • Expectation of Success: Using a well-known external testing technique to determine a circuit parameter was a routine and predictable process for a POSITA, who would have a high expectation of success.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that the Board should not exercise its discretion to deny institution under §314(a) or §325(d). It asserted that an inter partes review (IPR) was a more efficient and expedient forum than the co-pending district court litigation in the Western District of Texas. The petition highlighted the technical complexity of the obviousness grounds, which were better suited for the PTAB's technical expertise. Petitioner also noted uncertainty regarding the district court trial schedule and argued it had acted diligently in filing the IPR within weeks of the Patent Owner serving infringement contentions on a significant number of additional claims.

5. Relief Requested

• Petitioner requested institution of an IPR and cancellation of claims 1-13 and 15-16 of the ’373 patent as unpatentable under 35 U.S.C. §103.