Flex Logix Technologies Inc v. Konda Venkat

1. Case Identification

• Case #: IPR2020-00262
• Patent #: 8,269,523
• Filed: December 16, 2019
• Petitioner(s): Flex Logix Technologies, Inc.
• Patent Owner(s): Venkat Konda
• Challenged Claims: 1, 15-18, 20-22, 32, and 47

2. Patent Overview

• Title: VLSI Layouts of Fully Connected Generalized Networks
• Brief Description: The ’523 patent discloses layouts for multi-stage hierarchical networks, such as field-programmable gate arrays (FPGAs), that utilize horizontal and vertical cross-links between switches in successive stages. The invention purports to provide more efficient and less complicated network layouts than the prior art.

3. Grounds for Unpatentability

Ground 1: Anticipation over Wong - Claims 1 and 20-22 are anticipated by Wong under pre-AIA 35 U.S.C. § 102(b).

• Prior Art Relied Upon: Wong (Patent 6,940,308).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Wong, which discloses a scalable FPGA architecture based on a Benes network topology, teaches every limitation of independent claim 1 and its dependent claims 20-22. Petitioner contended that the claimed "plurality of sub-integrated circuit blocks" corresponds to the rows of switches and associated logic cells disclosed in Wong's figures (e.g., FIG. 13A). Wong was shown to disclose a two-dimensional grid of these blocks with both "straight links" (connecting switches within the same row/block) and "cross links" (connecting switches in different rows/blocks). Critically, Petitioner asserted that the examiner erred during prosecution by accepting the Patent Owner's misrepresentation that Wong's architecture could only be scaled by adding columns. Petitioner pointed to explicit disclosure in Wong stating that "the number of rows can also independently be any power of 2," demonstrating that the sub-integrated circuit blocks are replicable in both vertical and horizontal directions, thus meeting the key limitations added during prosecution to overcome Wong. Dependent claims 20-22, which recite arbitrary hardware logic, mask-programmable gate arrays (MPGAs), and ASICs, were also argued to be expressly disclosed in Wong.

Ground 2: Obviousness over Wong - Claims 15-18, 32, and 47 are obvious over Wong under pre-AIA 35 U.S.C. § 103.

• Prior Art Relied Upon: Wong (Patent 6,940,308).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that the features recited in the challenged dependent claims would have been obvious modifications to the architecture disclosed in Wong. For claim 15, Petitioner contended that the overlapping cross-links shown in Wong’s figures would necessitate the use of two or more metal layers to avoid short circuits, a standard and predictable design choice for a POSITA. For claim 16, because Wong expressly disclosed SRAM-based FPGAs, it would have been obvious to use SRAM cells to store configuration bits for the reprogrammable crosspoints. For claim 17, using sub-integrated circuit blocks of "equal die size" was presented as a mere design choice among a finite number of known alternatives, which a POSITA would have found beneficial for design efficiency and uniformity. For claim 47, Petitioner asserted that Wong discloses long routing lines, and adding buffers to reduce signal propagation delay on such lines was a well-understood, conventional solution in circuit design.
  • Motivation to Combine: The motivation was not to combine distinct references but to apply well-known principles to the Wong architecture. The motivation to use multiple metal layers was to implement the disclosed routing topology without creating electrical shorts. The motivation to add buffers was to improve signal timing and integrity, a predictable problem in any scalable network with long interconnects as taught by Wong.
  • Expectation of Success: Petitioner argued a POSITA would have had a high expectation of success because implementing features like multi-layer metal routing, SRAM-based control, and signal buffering were all standard, routine, and predictable techniques in integrated circuit design at the time.

4. Key Technical Contentions (Beyond Claim Construction)

• Interpretation of "Sub-Integrated Circuit Block": A central contention was that the Patent Owner improperly characterized Wong's disclosure during prosecution by arguing the entirety of Wong's FIG. 13A constituted a single "sub-integrated circuit block." Petitioner argued that a POSITA, reading the ’523 patent and Wong, would understand a "sub-integrated circuit block" to be a single row of switches and its associated logic. This interpretation was crucial because it established that Wong's cross-links connect different blocks, directly mapping to the claim language and refuting the basis for allowance.

5. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under § 325(d) would be inappropriate. Although the examiner considered Wong during prosecution, Petitioner contended the examiner "simply erred" by failing to recognize the relevance of specific portions of Wong to the limitations added by amendment. Petitioner asserted that its arguments and mapping, supported by new expert testimony not previously before the examiner, presented Wong in a new light that overcomes the prosecution history.

6. Relief Requested

• Petitioner requests institution of an IPR and cancellation of claims 1, 15-18, 20-22, 32, and 47 of the ’523 patent as unpatentable.