Intel Corp v. VLSI Technology LLC

1. Case Identification

• Case #: IPR2020-00498
• Patent #: 7,725,759
• Filed: February 4, 2020
• Petitioner(s): Intel Corporation
• Patent Owner(s): VLSI Technology LLC
• Challenged Claims: 12, 18-22, 24, 26-27

2. Patent Overview

• Title: Managing Clock Frequency in an Electronic Device
• Brief Description: The ’759 patent discloses a system for managing power and performance in an electronic device by selectively adjusting clock frequencies. The invention centers on a first "master device" that requests a change to a high-speed clock frequency in response to a predefined change in its own performance, with a clock controller then providing the high-speed clock to a second master device and a shared bus.

3. Grounds for Unpatentability

Ground 1: Obviousness over Chen, Terrell, and Rusu - Claim 12 is obvious over Chen in view of Terrell and Rusu.

• Prior Art Relied Upon: Chen (Patent 5,838,995), Terrell (Application # 2004/0098631), and Rusu (Application # 2003/0065960).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Chen taught the core limitations of claim 1, including monitoring multiple master devices on a bus and receiving a request from a first master device to change a clock frequency. Chen’s system, however, based this request on the device’s inherent capability. Petitioner asserted Terrell taught modifying this system by making the request responsive to a predefined change in performance, specifically by measuring processor workload over a sample period to determine the needed clock speed. For claim 12, Petitioner contended Rusu taught the claimed feature of the performance change comprising a change in power consumption, as Rusu disclosed a power sensor that monitors processor power consumption to determine optimal frequency.
  • Motivation to Combine: A POSITA would combine Chen with Terrell to improve power efficiency. Chen’s capability-based system could use more power than necessary, whereas Terrell’s need-based system adjusts frequency to the minimum required for the current workload, a known method for power conservation. A POSITA would further add Rusu’s power-sensing technique as another well-known trigger for adjusting clock frequency to further optimize power savings, a desirable goal in such systems.
  • Expectation of Success: The combination involved applying known, predictable techniques (workload and power monitoring) to a known system architecture (multi-master device bus) to achieve the expected benefit of improved power management.

Ground 2: Obviousness over Chen, Terrell, and Kiriake - Claims 18, 20-22, 24, and 27 are obvious over Chen in view of Terrell and Kiriake.

• Prior Art Relied Upon: Chen (Patent 5,838,995), Terrell (Application # 2004/0098631), and Kiriake (Application # 2003/0159080).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground challenged system claims corresponding to the method of Ground 1. Petitioner argued the combination of Chen and Terrell taught most limitations of independent claim 18 for the same reasons as Ground 1. The key additional element in claim 18 was an "arbiter configured to control flow of data on the bus." Petitioner asserted that Kiriake taught this element, disclosing an arbiter that manages bus requests and grants access to multiple processors.
  • Motivation to Combine: A POSITA would have been motivated to incorporate Kiriake's arbiter into Chen's multi-master system. Chen's system inherently required arbitration to manage bus access between its multiple master devices. Adding an explicit arbiter like Kiriake’s to a central bus controller was a well-known and standard design practice for managing bus traffic and preventing conflicts, making it a desirable and logical addition to Chen’s architecture.
  • Expectation of Success: Since Chen, Terrell, and Kiriake all described similar multi-processor bus systems, combining a standard arbiter (Kiriake) with such a system (Chen/Terrell) was a straightforward substitution of known elements that would yield the predictable result of properly managed bus access.

Ground 3: Obviousness over Shaffer, Lint, and Rusu - Claim 12 is obvious over Shaffer in view of Lint and Rusu.

• Prior Art Relied Upon: Shaffer (Patent 6,298,448), Lint (Patent 7,360,103), and Rusu (Application # 2003/0065960).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner presented Shaffer as an alternative primary reference that disclosed a system where a CPU requests changes to a clock frequency based on CPU utilization. Petitioner argued that Lint taught the claimed limitation of the request being "due to loading...as measured within a predefined time interval," as Lint described calculating an "average performance" based on cycles spent doing useful work during a "predetermined interval." For claim 12, Rusu was again relied upon to teach that the change in performance could be a change in power consumption.
  • Motivation to Combine: A POSITA would combine Lint with Shaffer to provide a more concrete and improved method for implementing Shaffer’s CPU utilization monitoring. While Shaffer mentioned monitoring utilization, Lint provided a specific, known technique for doing so. As both references aimed to save power by adjusting clock frequency, this combination represented a natural evolution of known monitoring programs. Rusu’s power-sensing feature would be added for the same reason: to provide an additional, complementary metric for optimizing power consumption.
  • Expectation of Success: A POSITA would have had a reasonable expectation of success in combining Lint's detailed performance measurement technique with Shaffer’s system, as it was an application of a known monitoring improvement to a similar system for the predictable purpose of saving power.

• Additional Grounds: Petitioner asserted additional obviousness challenges for claims 19 and 26 based on combinations of Chen/Terrell/Kiriake/Rusu and Shaffer/Lint/Kiriake/Rusu, relying on similar arguments for combining the respective art.

4. Arguments Regarding Discretionary Denial

• Petitioner argued against discretionary denial under §314(a) and §325(d). It contended that this second petition was filed diligently within five weeks of the Patent Owner asserting new claims in amended infringement contentions in a co-pending district court case. Petitioner asserted there was no overlap in the challenged claims between its first and second petitions. It further argued that an inter partes review (IPR) is a more efficient and expert forum for the complex multi-reference obviousness arguments presented compared to a jury trial in the Western District of Texas. Finally, Petitioner noted that the district court trial schedule was uncertain and that a Final Written Decision could issue before a final, appealable judgment from the court.

5. Relief Requested

• Petitioner requested institution of an IPR and cancellation of claims 12, 18-22, 24, and 26-27 of the ’759 patent as unpatentable.