PTAB

IPR2020-00525

Intel Corp v. PACT XPP Schweiz AG

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Integrated Circuit Data Processor with Defective Core Management
  • Brief Description: The ’505 patent describes an integrated circuit (IC) data processor containing multiple processing cores. The technology provides a system for detecting, disabling, and replacing defective cores with redundant ones to improve manufacturing yields and ensure operational integrity.

3. Grounds for Unpatentability

Ground 1: Claims 1 and 27 are obvious over Ivey

  • Prior Art Relied Upon: Ivey (The ELSA Wafer Scale Integration Project, Pub. 1993).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Ivey, describing the European Large SIMD Array (ELSA) project, teaches all limitations of independent claims 1 and 27. Ivey’s “array processor on a 4-in wafer” was asserted to be an IC data processor with an array of processing elements (PEs), satisfying the “data processing cores” limitation. Petitioner contended that each PE in Ivey contains an Arithmetic and Logic Unit (ALU) and that Ivey’s “autonomous test program” performs a self-test on each PE. Defective PEs are disabled by disconnecting them from the processor array via a bypass switching network, meeting the self-test and disable limitations of claim 1. For claim 27, Petitioner argued Ivey's communication bus and 7x12 PE array (which includes one redundant column, resulting in 84 implemented cores versus 72 used cores) satisfy the limitations requiring a bus system, a >2x2 array, and implementing more cores than are used.

Ground 2: Claim 5 is obvious over Ivey in view of Campbell

  • Prior Art Relied Upon: Ivey (The ELSA Wafer Scale Integration Project, Pub. 1993) and Campbell (Hierarchical Fault Tolerance for 3D Microelectronics, Pub. 1990).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner relied on Ivey to teach the base limitations of claim 1 and introduced Campbell to teach the dependent claim 5 limitation of detecting defective cores "in the field." Campbell was asserted to teach fault tolerance as the ability to handle failures "during the operation of the computer after" assembly. This capability to detect failures during runtime, rather than only during manufacture, allegedly meets the "detected in the field" limitation.
    • Motivation to Combine: A POSITA would combine the references because both address the same problem of defect tolerance in multi-processor ICs. A POSITA would be motivated to extend Ivey’s manufacturing-stage testing to include Campbell’s post-assembly, operational testing to prevent in-field failures, thereby enhancing the processor’s overall utility and reliability.
    • Expectation of Success: The combination was presented as a predictable extension of a known testing methodology. Applying testing procedures to the operational phase of a device’s life cycle was a logical and well-understood step for improving system robustness, leading to a high expectation of success.

Ground 3: Claims 12-18 are obvious over Hsu, or Hsu in view of Lakkapragada and/or Morton

  • Prior Art Relied Upon: Hsu (Patent 5,498,886), Lakkapragada (Defect-Tolerant Processor Arrays, Pub. 1995), and Morton (Patent 4,783,782).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Hsu’s "wafer-scale integration device" discloses an IC with an array of "circuit modules" (data processing cores). Hsu teaches that a "disable switch," which can be implemented using non-volatile memory (NVM) such as fuses or EPROM cells, can switch off a defective core. Petitioner asserted this NVM stores the defect information and that the core is disabled as a function of that information, meeting the primary limitations of independent claims 12, 14, 16, and 18. To meet the limitation of processing "different instructions at a single time," Petitioner introduced Lakkapragada for its explicit teaching of a multiple-instruction, multiple-data (MIMD) processor array. As an alternative for NVM teachings, Petitioner cited Morton for its disclosure of storing defect information in a programmable read-only memory (PROM).
    • Motivation to Combine: A POSITA would combine Hsu with Lakkapragada to improve Hsu’s parallel processing system, as Lakkapragada teaches that MIMD architecture is highly successful for large-scale systems. The combination with Morton was motivated by the desire to use a conventional and economical method (a PROM) for storing defect patterns in Hsu's system. Both combinations address the shared problem of defect tolerance.
    • Expectation of Success: Substituting a known MIMD architecture for a SIMD architecture was a predictable design choice with established benefits. Likewise, incorporating a PROM as taught by Morton to manage defect data was a straightforward application of a well-known technique, giving a POSITA a reasonable expectation of success for both combinations.
  • Additional Grounds: Petitioner asserted additional obviousness challenges based on combinations of Ivey with Morton, van der Have, and Lakkapragada, and Hsu with Lakkapragada, to address specific limitations such as using non-volatile memory to store defect patterns, detecting defects at system start, and specific bus and array configurations.

4. Relief Requested

  • Petitioner requests institution of inter partes review (IPR) and cancellation of claims 1, 3, 5, 7-8, 12-18, and 27 of the ’505 patent as unpatentable.