Intel Corp v. VLSI Technology LLC

1. Case Identification

• Case #: IPR2020-00526
• Patent #: 6,633,187
• Filed: February 13, 2020
• Petitioner(s): Intel Corporation
• Patent Owner(s): VLSI Technology LLC
• Challenged Claims: 2-8, 10, and 11

2. Patent Overview

• Title: Power on Reset Techniques for an Integrated Circuit Chip
• Brief Description: The ’187 patent relates to methods and systems for applying a power-on-reset sequence to a stand-alone integrated circuit (IC) that includes an on-chip power converter. The technique ensures that functional circuitry remains idle until the on-chip converter generates a stable supply voltage.

3. Grounds for Unpatentability

Ground I: Claims 2-5 and 7 are obvious over Page, Stratakos, Bujanos, and LeWalter

• Prior Art Relied Upon: Page (Patent 6,980,037), Stratakos (a Ph.D. thesis on DC-DC conversion), Bujanos (Patent 5,949,227), and LeWalter (Patent 5,739,708).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Page, the primary reference, disclosed the core method of the ’187 patent: a power-on-reset technique for an IC with an on-chip switching converter. Page taught establishing an idle state by inhibiting clocks until voltage stability is achieved. However, Page allegedly lacked specific implementation details for the converter's control circuitry. Stratakos was introduced to teach using a system clock (like Page’s phase-locked loop (PLL) clock) to generate regulation signals for a switching converter. Bujanos was added to teach enabling a band-gap reference via an enable signal to generate the regulation signals, a common technique for power savings. Finally, LeWalter was combined to supply the teaching of using an explicit reset signal to establish the idle state, a detail Petitioner argued was not fully elaborated in Page.
  • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine these references for clear reasons. Page itself expressly cited a conference paper by Stratakos on the same topic as his thesis, directly motivating a POSITA to consult Stratakos for details on switching converters. A POSITA would incorporate Bujanos’s teachings on enabling a band-gap reference to achieve power savings, a well-known goal in IC design and one mentioned in Page. LeWalter would be consulted to implement the idle state, as both it and Page relate to power-on-reset techniques, and Page’s examiner had cited LeWalter during prosecution.
  • Expectation of Success: Petitioner asserted a high expectation of success, as combining these elements involved applying known techniques (e.g., using band-gap references, clock-driven converters, reset signals) to solve predictable problems in IC design, yielding no unexpected results.

Ground II: Claim 6 is obvious over Page, Stratakos, Bujanos, and Goder

• Prior Art Relied Upon: Page (Patent 6,980,037), Stratakos, Bujanos (Patent 5,949,227), and Goder (Patent 5,617,015).

• Core Argument for this Ground:

  • Prior Art Mapping: This ground challenged claim 6, which adds the limitation of generating first and second supplies from a single inductor. Petitioner argued that the base combination of Page, Stratakos, and Bujanos taught all elements of claim 1. Goder was added to explicitly teach a switching voltage regulator that provides multiple, independently regulated outputs from a single inductor and power source. Petitioner contended that Goder's circuit, which uses a main switch and multiple auxiliary switches to direct energy from one inductor to different outputs, directly mapped onto the claim 6 limitation.
  • Motivation to Combine: A POSITA would be motivated to modify Page’s converter with Goder’s multi-output, single-inductor design to meet the increasing industry demand for ICs requiring multiple voltage levels. Providing different voltages to different components was a known method for power saving (e.g., dynamic voltage and frequency scaling), which aligned with the design goals of Page. Modifying Page's single-output converter to be a multi-output one as taught by Goder was presented as a logical step to improve power efficiency.
  • Expectation of Success: Petitioner claimed a reasonable expectation of success because switching converters were well-known, and Goder disclosed that its regulator could be implemented as an integrated circuit. A POSITA would have found it straightforward to integrate Goder’s known multi-output topology into Page's IC design.

• Additional Grounds: Petitioner asserted additional obviousness challenges, including for claim 8 over combinations including Yasuda (Patent 5,936,443) to teach detecting a supply lock signal, and for claims 10 and 11 based on similar combinations of the primary references.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under §314(a) or §325(d) would be inappropriate. First, the petition raised new grounds and prior art not used in two earlier petitions, which were filed to address a staggered assertion of claims by the Patent Owner in district court. Second, Petitioner argued that the IPR forum is more efficient and effective for the complex technical issues of IC design than a jury trial. Third, given the parallel district court litigation schedule, a Final Written Decision (FWD) from the PTAB could issue before a final appealable judgment from the court, promoting efficiency.

5. Relief Requested

• Petitioner requested institution of an inter partes review and cancellation of claims 2-8, 10, and 11 of the ’187 patent as unpatentable under 35 U.S.C. §103.