Intel Corp v. PACT XPP Schweiz AG

1. Case Identification

• Case #: IPR2020-00542
• Patent #: 9,170,812
• Filed: February 7, 2020
• Petitioner(s): Intel Corporation
• Patent Owner(s): PACT XPP Schweiz AG
• Challenged Claims: 1-5, 8, 9, 12-18

2. Patent Overview

• Title: Multiprocessor Architecture with Shared Resources
• Brief Description: The ’812 patent relates to a multiprocessor architecture on a single integrated circuit. The system comprises a data processor core and an array data processor that share resources, including a joint cache connected to memory.

3. Grounds for Unpatentability

Ground I: Obviousness of Claim 1 over Song, alternatively in view of Gove

• Prior Art Relied Upon: Song (Patent 5,996,058) and Gove (Patent 6,948,050).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Song, which discloses a multiprocessor system, teaches all elements of claim 1. Song’s system includes a control processor (the claimed “data processor core”) and a vector processor (the claimed “array data processor”) that contains an array of ALUs for parallel execution. These processors share a cache subsystem (the claimed “joint cache”) connected to memory. An instruction fetch unit and decoder/issuer within Song's vector processor function as the claimed "algorithm loader."
  • Motivation to Combine (for §103 grounds): To the extent Song does not explicitly teach implementing its multiprocessor system on a single integrated circuit, Petitioner asserted a POSITA would combine Song with Gove. Gove teaches integrating RISC and DSP processors onto a single chip to solve the known complexity of interconnecting separate processors.
  • Expectation of Success (for §103 grounds): A POSITA would have a reasonable expectation of success in placing Song's components on a single chip as taught by Gove to achieve the predictable benefit of a more compact and efficient design.

Ground II: Obviousness of Claims 2, 3, 5, and 13-18 over Song and Gove, in further view of Arimilli and Houston

• Prior Art Relied Upon: Song (Patent 5,996,058), Gove (Patent 6,948,050), Arimilli (Patent 6,748,501), and Houston (Patent 5,615,162).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground builds upon the combination of Song and Gove to address dependent claims requiring a cache hierarchy and an adaptable-size cache. Petitioner argued Arimilli teaches a multi-level cache (L1/L2) where the L2 cache is divided into slices, satisfying limitations for a cache hierarchy. Houston teaches a method for reducing power consumption by dividing a cache into memory blocks and selectively providing power to them, thereby making the cache "adaptable in size" as required by the claims.
  • Motivation to Combine (for §103 grounds): A POSITA would combine Arimilli with the Song/Gove system to improve cache performance, a well-known objective. Adding multi-level, sliced caches was a known technique for improving read/write efficiency. A POSITA would further add Houston's power-saving technique to the system to reduce power consumption and leakage current, another common design goal. Houston’s adaptable memory blocks were seen as a straightforward application to Arimilli’s cache slices.
  • Expectation of Success (for §103 grounds): Integrating these known cache improvements (multi-level architecture from Arimilli, power-saving from Houston) into a standard multiprocessor system like Song's was a simple substitution of known elements to achieve predictable results in performance and power efficiency.

Ground III: Obviousness of Claim 1 over Miyamori, alternatively in view of Gove

• Prior Art Relied Upon: Miyamori (a 1998 technical publication) and Gove (Patent 6,948,050).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner presented Miyamori as an alternative primary reference that renders claim 1 obvious. Miyamori discloses a microprocessor architecture with a main processor (the “data processor core”) and a reconfigurable coprocessor called REMARC (the “array data processor”). The REMARC is an 8x8 array of nano-processors (arithmetic execution units) that execute instructions in parallel. The main processor and REMARC share a data cache, which is inherently connected to memory to handle cache misses. A global control unit in Miyamori functions as the "algorithm loader."
  • Motivation to Combine (for §103 grounds): Similar to the argument in Ground I, Petitioner asserted that if Miyamori was not considered to teach a single integrated circuit, a POSITA would combine its teachings with Gove. The motivation remains to overcome interconnection problems and create a more efficient, integrated design.
  • Expectation of Success (for §103 grounds): A POSITA would expect success in integrating Miyamori’s processor and coprocessor onto a single chip for the predictable benefits taught by Gove.
• Additional Grounds: Petitioner asserted numerous additional obviousness challenges based on combinations of Song or Miyamori with secondary references. These grounds used Arimilli, Houston, Bogin (Patent 5,835,435), and Wilson (Patent 4,755,930) to address specific dependent claim limitations related to multi-level caches, cache slicing, adaptable cache size, power-saving via clock control, and dedicated L1 caches.

4. Key Claim Construction Positions

• Petitioner argued that the term “instruction dispatch unit…configured to dispatch software threads” (claims 12-18) is subject to 35 U.S.C. §112, paragraph 6, and should be limited to the corresponding configuration unit (CT) disclosed in the ’812 patent’s specification.
• However, Petitioner contended that the Board did not need to formally construe this or any other term, as the challenged claims are unpatentable under either the Patent Owner’s plain and ordinary meaning or Petitioner’s proposed construction.

5. Arguments Regarding Discretionary Denial

• Petitioner argued that this IPR is not redundant of the original examination and should not be denied under §325(d).
• It was asserted that none of the grounds or prior art references presented in the petition were considered by the Examiner during prosecution. Petitioner further noted that the Patent Owner had submitted over 300 prior art references to the Examiner under a Track One expedited review, which likely prevented a thorough consideration of the most relevant art.

6. Relief Requested

• Petitioner requested institution of an inter partes review and cancellation of claims 1-5, 8, 9, and 12-18 of the ’812 patent as unpatentable.