PTAB

IPR2020-00989

Advanced Micro Devices Inc v. Monterey Research LLC

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1. Case Identification

2. Patent Overview

  • Title: Programmable Digital Circuit Block
  • Brief Description: The ’407 patent discloses a programmable digital circuit block designed to improve upon conventional Field Programmable Gate Arrays (FPGAs). The technology aims to overcome FPGA drawbacks such as long configuration times and inefficient chip area usage by providing a block that can be quickly programmed to perform one of a variety of predetermined digital functions by writing a small number of configuration bits to registers.

3. Grounds for Unpatentability

Ground 1: Claims 1, 7-8, 14-15 are anticipated by Mitra, and Claims 1-3, 6-10, 13-17, and 20 are obvious over Mitra.

  • Prior Art Relied Upon: Mitra (Patent 5,577,235)
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Mitra discloses every element of the challenged claims. Mitra teaches a microcontroller with multiple "CCP" (Capture/Compare/PWM) modules, which are programmable digital circuit blocks. Each CCP module is configurable to perform one of three predetermined digital functions (capture, compare, or pulse-width modulation) by writing to a single 8-bit control register (CCPxCON). This single register write operation selects the desired function and configures its operational details, directly mapping to the limitations of independent claims 1, 8, and 15. Petitioner further argued that Mitra’s disclosure of using multiple CCP modules on a single chip constitutes the claimed "array" of such blocks.
    • Motivation to Combine (for §103 grounds): For the obviousness contentions based solely on Mitra, Petitioner argued that Mitra explicitly teaches that its multiple CCP modules can be flexibly configured for a user's particular application. A person of ordinary skill in the art (POSITA) would have found it obvious to configure these modules into basic serial or parallel arrangements, as these are fundamental circuit design choices. For example, Mitra’s discussion of applications like anti-skid braking systems (requiring multiple capture inputs) suggests parallel configurations, while other signal processing tasks would naturally suggest serial arrangements.
    • Expectation of Success (for §103 grounds): A POSITA would have had a high expectation of success in implementing Mitra’s teachings and making obvious variations, as the design and use of microcontrollers and standard digital functions were well within the ordinary skill in the art.

Ground 2: Claims 3, 8, 10, 13-14, and 17 are obvious over Mitra in view of Munro.

  • Prior Art Relied Upon: Mitra (Patent 5,577,235) and Munro (Patent 5,506,484)
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon Mitra by adding Munro to explicitly teach configuring programmable blocks in a parallel arrangement. Mitra provided the configurable CCP modules, and Munro disclosed a digital pulse-width modulation (PWM) application for three-phase motor control that uses three comparators configured in parallel. The combination allegedly rendered claims requiring a parallel arrangement (claims 3, 10, 17) obvious.
    • Motivation to Combine (for §103 grounds): Petitioner asserted a strong motivation to combine these references. Mitra explicitly mentioned that its CCP modules were useful for automobile applications, including "three-phase motor control." Munro taught a specific, well-known implementation of such an application using parallel comparators. A POSITA seeking to apply Mitra’s flexible CCP modules to this known application would have been motivated to configure them in the parallel arrangement taught by Munro to achieve the desired functionality. The teachings were synergistic, as both references dealt with similar digital timing functions.
    • Expectation of Success (for §103 grounds): A POSITA would have had a reasonable expectation of success, as the combination involved applying a known module (Mitra's CCP) in a known configuration (Munro's parallel circuit) for a commonly understood application (motor control).

Ground 3: Claims 1-3, 6-10, 13-17, and 20 are obvious over Vorbach.

  • Prior Art Relied Upon: Vorbach (Patent 6,728,871)
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Vorbach, like the ’407 patent, identified and solved the same problems with conventional FPGAs. Vorbach taught a Processing Array (PA) composed of an array of Programmable Array Elements (PAEs). Each PAE contained an "expanded arithmetic and logic unit" (EALU) capable of performing a plurality of predetermined digital functions (e.g., counter, adder, logic functions). Critically, the function of the EALU was configured by a single function register (F-PLUREG), which greatly reduced the volume of configuration data required. Petitioner mapped Vorbach’s PAE/EALU to the claimed "programmable digital circuit block" and the F-PLUREG to the "single register write operation."
    • Motivation to Combine (for §103 grounds): This ground did not require a combination of references. The motivation for a POSITA to arrive at the claimed invention was inherent in Vorbach's own disclosure, which taught improving FPGAs with a module of predetermined functions configured by a single register. For dependent claims, Vorbach taught that its PAEs were "cascadable" and could be configured "freely over a bus system" for "serial operations" or broadcasting data to multiple receivers in parallel.
    • Expectation of Success (for §103 grounds): A POSITA would have had a high expectation of success in applying Vorbach's teachings, as Vorbach provided a detailed architecture and expressly stated its purpose was to create a more efficient, faster-to-configure alternative to conventional FPGAs, aligning perfectly with the purported invention of the ’407 patent.
  • Additional Grounds: Petitioner asserted an additional obviousness challenge based on Mitra in view of Evans (Patent 4,049,953). Evans was used to provide a specific motivation for a serial arrangement of programmable blocks, teaching a radar application where a comparator is connected in series with a pulse width generator.

4. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial would be improper. It was asserted that none of the prior art relied upon in the petition was considered during the original prosecution of the ’407 patent. Furthermore, this was the first IPR filed against the patent, and in the parallel district court litigation, no scheduling conference, Markman hearing, or trial date had been set, suggesting that an IPR would be an efficient resolution.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-3, 6-10, 13-17, and 20 of Patent 6,765,407 as unpatentable.