PTAB

IPR2020-01017

Advanced Micro Devices Inc v. Monterey Research LLC

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1. Case Identification

2. Patent Overview

  • Title: Multipurpose On-Chip Memory for Integrated Circuits
  • Brief Description: The ’807 patent relates to an integrated circuit device featuring a multipurpose memory that can be configured to operate in two distinct modes. A first mode serves as a cache memory for dynamically storing portions of a program from a first external memory device, while a second mode is for storing an entire program obtained from a second external memory device.

3. Grounds for Unpatentability

Ground 1: Claims 1-4 and 7-17 are obvious over Saulsbury in view of Cullison.

  • Prior Art Relied Upon: Saulsbury (Application # 2002/0087821) and Cullison (Patent 5,155,833).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Saulsbury teaches the core structure of the challenged claims: an integrated circuit with a microprocessor, an on-chip multipurpose memory (DRAM), a cache controller, a first port for external memory, and a second port for a boot interface. Petitioner asserted that Cullison teaches using a similar multipurpose memory (SRAM) in two distinct operating modes as claimed: a first mode to store an entire boot program during system initialization and a second mode to act as a cache memory during normal operation.
    • Motivation to Combine: A POSITA would combine Cullison’s dual-mode memory teachings with Saulsbury’s more advanced processor architecture to achieve predictable benefits. Applying Cullison’s boot-mode functionality to Saulsbury’s on-chip memory would improve bootup times by loading the program into faster on-chip memory. Subsequently using that same memory as a cache would reduce latency and lower overall system cost by eliminating the need for separate memory components.
    • Expectation of Success: Petitioner contended that a POSITA would have a reasonable expectation of success in making this combination. The constituent components—on-chip memory, cache controllers, and memory ports—were conventional, and applying a known technique (dual-mode memory) to improve a known device (a processor) would yield predictable results.

Ground 2: Claims 1-4 and 7-17 are obvious over Kumar in view of Cullison.

  • Prior Art Relied Upon: Kumar (Patent 5,970,069) and Cullison (Patent 5,155,833).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Kumar, like Saulsbury, teaches an integrated circuit (a "RAP chip") with a microprocessor, on-chip multipurpose memory (SRAM), a first port to local memory (e.g., DRAM), and a second port (a PCI bus interface) to a host system. The teachings of Cullison regarding a multipurpose memory operating in distinct boot and cache modes were applied in the same manner as in Ground 1.
    • Motivation to Combine: The motivation to combine Kumar and Cullison was analogous to that for Ground 1. A POSITA would be motivated to improve the performance of Kumar's RAP chip by applying Cullison's well-understood dual-mode memory technique. This would improve performance by reducing memory latency during both bootup and normal operation, reflecting an industry trend toward increased integration and on-chip optimization.
    • Expectation of Success: Success would be reasonably expected because the combination involves applying a known memory optimization from Cullison to a standard processor architecture in Kumar. Both references are from the same field, and the combination uses conventional components for their known purposes.

Ground 3: Claim 5 is obvious over Saulsbury, Cullison, and Gupta.

  • Prior Art Relied Upon: Saulsbury (Application # 2002/0087821), Cullison (Patent 5,155,833), and Gupta (Patent 5,996,083).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground builds on the combination of Saulsbury and Cullison from Ground 1 to address claim 5, which recites that the second memory port is not coupled when the first memory port is active. Petitioner argued that Gupta teaches a method for reducing power consumption in a microprocessor by shutting down and electrically disconnecting functional units, including memory ports, that are not currently in use.
    • Motivation to Combine: A POSITA would combine Gupta's power-saving teachings with the primary combination for the clear benefit of reducing power consumption. In the proposed Saulsbury/Cullison device, the second memory port (the boot interface) is idle after the boot process is complete and the memory is operating in cache mode. A POSITA would find it obvious to apply Gupta’s technique to disable this unused port to save power, a common and important design consideration.
    • Expectation of Success: This modification would have a high expectation of success, as disabling unused components to conserve power was a widely-known and practiced technique in integrated circuit design.

  • Additional Grounds: Petitioner asserted an additional obviousness challenge against claim 5 based on the combination of Kumar, Cullison, and Gupta, relying on the same power-saving motivation and design modification theories.

4. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial would be inappropriate. It was asserted that none of the prior art references relied upon in the petition were considered during the original prosecution of the ’807 patent. Furthermore, Petitioner stated that this was the first IPR proceeding filed against the patent and that the parallel district court litigation was in its early stages, with no scheduling conference, claim construction hearing, or trial date set.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-17 of Patent 6,961,807 as unpatentable.