PTAB

IPR2020-01020

Samsung Electronics Co Ltd v. Arbor Global Strategies LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Stacked Processor Module
  • Brief Description: The ’035 patent discloses a reconfigurable processor module formed by vertically stacking different types of integrated circuit dies, such as FPGAs, microprocessors, and memory. The dies are electrically interconnected by a number of contact points, such as through-silicon vias (TSVs), that are distributed throughout the surfaces of the dies and traverse their thickness.

3. Grounds for Unpatentability

Ground 1: Anticipation of Claims 1, 5, and 7 under 35 U.S.C. §102 by Alexander

  • Prior Art Relied Upon: Alexander (Alexander et al., Three-Dimensional Field-Programmable Arrays, IEEE 1995).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Alexander discloses every element of independent claim 1. Alexander teaches a 3D FPGA processor module built by stacking multiple 2D FPGA bare dies to improve performance and reduce size. It explicitly discloses that "each individual die... has vias passing through the die itself" and uses solder bumps distributed across the die surfaces to implement "vertical interconnections between layers." This structure meets the claim limitations of a first die (FPGA) stacked with a second die, electrically coupled by contact points (vias and bumps) distributed throughout the surfaces and traversing the die thickness. Petitioner asserted that Alexander also discloses stacking a third die, anticipating claim 5, and teaches that the FPGAs are reconfigurable processing elements, anticipating claim 7.

Ground 2: Obviousness of Claims 1, 3, 5-9, 11, 13-17, 19-22, 25, 26, 28, and 29 under 35 U.S.C. §103 over Koyanagi in view of Alexander

  • Prior Art Relied Upon: Koyanagi (Koyanagi et al., Future System-on-Silicon LSI Chips, IEEE 1998) and Alexander.
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner contended that Koyanagi teaches a universal 3D-integration technology for stacking heterogeneous bare dies—such as microprocessors, SRAM, and DRAM—using a high density of TSVs ("buried interconnections") and microbumps distributed across the chip surfaces. Alexander teaches the specific benefits of building 3D FPGAs using a nearly identical stacking method to reduce interconnect delay. The combination renders obvious a processor module comprising a stacked FPGA, microprocessor, and memory die, as claimed.
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine Koyanagi’s universal heterogeneous stacking method with Alexander’s specific teaching of stacked FPGAs to create a compact, high-performance reconfigurable processor. This combination would achieve the well-known benefits of 3D integration (miniaturization, lower power, reduced latency) for the known architecture of an FPGA-based computer system, which the ’035 patent itself admits was conventional.
    • Expectation of Success: A POSITA would have had a reasonable expectation of success because both Koyanagi and Alexander teach the same fundamental 3D integration scheme: stacking bare dies interconnected with distributed TSVs. Applying Koyanagi's method for stacking different die types (processor, memory) to Alexander’s stacked FPGAs was presented as a predictable design choice, not an inventive step.

Ground 3: Obviousness of Claims 1, 3, 5-9, 11, 13-17, 19-22, 25, 26, 28, and 29 under 35 U.S.C. §103 over Bertin in view of Cooke

  • Prior Art Relied Upon: Bertin (Patent 6,222,276) and Cooke (Patent 5,970,254).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner asserted that Bertin teaches a universal 3D integration scheme for stacking various chip types, including logic chips, microprocessors, and controllers, using "through-chip conductors" (TSVs) distributed across the die to achieve high-performance inter-chip communication. Cooke discloses a 2D reconfigurable processor system that integrates a standard processor, FPGA logic, and a "vertical stack" of memory planes.
    • Motivation to Combine: A POSITA would be motivated to apply Bertin's universal 3D stacking technology to the discrete functional components described in Cooke's 2D system (FPGA, processor, memory). The motivation was to achieve the known benefits of 3D integration, such as higher packing densities and improved performance by eliminating the interconnect delays inherent in the 2D FPGA-based systems that Cooke represents.
    • Expectation of Success: Success would be expected because Bertin provides a broadly applicable and detailed teaching for stacking the exact types of components used in Cooke’s system. Stacking the elements of Cooke's known reconfigurable system using Bertin's known 3D integration method would have been a straightforward engineering task to achieve predictable improvements.

  • Additional Grounds: Petitioner asserted an additional obviousness challenge for claims 9, 13, and 15 based on the Admitted Prior Art (APA) in the ’035 patent in view of Alexander.

4. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under 35 U.S.C. §325(d) is unwarranted because the primary prior art references (Koyanagi, Alexander, Bertin, Cooke) and the specific combinations asserted were never presented to or considered by the Examiner during prosecution.
  • Petitioner further argued that discretionary denial under 35 U.S.C. §314(a) based on Fintiv factors would be inappropriate. At the time of filing, the parallel district court case was in its early stages, with infringement contentions recently served and claim construction not scheduled to begin for several months, ensuring that an IPR would be a more efficient resolution.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1, 3, 5-9, 11, 13-17, 19-22, 25, 26, 28, and 29 of the ’035 patent as unpatentable.