PTAB

IPR2020-01021

Samsung Electronics Co Ltd v. Arbor Global Strategies LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Reconfigurable Processor Module with Stacked Dies
  • Brief Description: The ’951 patent describes a reconfigurable processor module formed by vertically stacking different types of integrated circuit dies, such as FPGAs, microprocessors, and memory. The dies are interconnected using through-silicon contacts (TSVs) that are distributed across the entire surfaces of the dies to improve performance and reduce size.

3. Grounds for Unpatentability

Ground I: Obviousness over Koyanagi in view of Alexander - Claims 1, 4, 5, 8, 10, 13-15 are obvious over Koyanagi in view of Alexander.

  • Prior Art Relied Upon: Koyanagi (an IEEE 1998 article titled “Future System-on-Silicon LSI Chips”) and Alexander (an IEEE 1995 article titled “Three-Dimensional Field-Programmable Arrays”).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Koyanagi taught a universal three-dimensional integration technology for stacking bare dies of different types (e.g., microprocessor, SRAM, DRAM) using a high density of TSVs ("buried interconnections") and microbumps distributed across the chip surfaces. Alexander taught the specific application of this same 3D integration scheme to stack 2D FPGA bare dies, using "vias passing through the die itself" and distributed solder bumps to achieve smaller size and better performance. The combination of Koyanagi’s heterogeneous stack and Alexander’s FPGA element allegedly rendered the claims obvious. For claim 1, the combination taught a processor module (Koyanagi's stack) comprising a first programmable element (Alexander’s FPGA), a second stacked memory element (Koyanagi’s DRAM), coupled by contacts distributed throughout the surfaces (taught by both), with the memory functional to accelerate references via the high-bandwidth vertical interconnects explicitly disclosed by Koyanagi to solve 2D bus bottlenecks.
    • Motivation to Combine: A POSITA would combine Koyanagi’s universal 3D stacking framework with Alexander’s specific teaching of stacking FPGAs to create a 3D reconfigurable processor module. The motivation was to achieve the well-known benefits of 3D integration—such as miniaturization, lower power consumption, and improved performance—for a conventional reconfigurable computer system (FPGA, processor, memory). Koyanagi's scheme was agnostic to die type, and Alexander demonstrated that FPGAs were suitable for such 3D stacking.
    • Expectation of Success: A POSITA would have a reasonable expectation of success because both Koyanagi and Alexander taught the same fundamental 3D integration scheme using TSVs and distributed surface contacts. Applying Koyanagi's detailed method for stacking heterogeneous dies to an FPGA, as shown feasible by Alexander, would have been a predictable implementation.

Ground II: Obviousness over Bertin in view of Cooke - Claims 1, 4, 5, 8, 10, 13-15 are obvious over Bertin in view of Cooke.

  • Prior Art Relied Upon: Bertin (Patent 6,222,276) and Cooke (Patent 5,970,254).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner asserted that Bertin disclosed a universal 3D integration scheme for vertically stacking different types of chips—including logic chips, microprocessors, and memory—using through-chip conductors (TSVs) and distributed chip-to-chip connectors. Cooke described a 2D reconfigurable computer system architecture that integrated a processor, special FPGA logic, and a "vertical stack" of memory planes. Petitioner argued that a POSITA would have understood Bertin's "logic chip" to encompass FPGAs. The combination allegedly disclosed the claimed module: implementing Cooke's FPGA, processor, and memory components using Bertin’s 3D stacking technology would result in a module with a first programmable element (FPGA from Cooke), a second stacked memory element (memory from Cooke), coupled by distributed contact points (the core of Bertin’s teaching). The acceleration feature was met by Bertin's high-performance inter-chip communication, which was designed to increase performance by connecting array lines directly between chips.
    • Motivation to Combine: A POSITA would be motivated to apply Bertin’s advanced and universal 3D integration teachings to the functional components of the reconfigurable computer system described in Cooke. The objective would be to improve performance and area efficiency over the 2D-based systems of the prior art by overcoming known issues like interconnect delay, thereby achieving the high packing densities and improved communication speeds explicitly taught by Bertin.
    • Expectation of Success: There was a reasonable expectation of success because Bertin’s stacking technology was designed to be universal and "accommodate different chip sizes and structures." Applying this flexible 3D method to the well-defined set of components in Cooke's system (FPGA, processor, memory) would be a straightforward implementation of known components using an available, improved integration technique.

4. Arguments Regarding Discretionary Denial

  • §325(d) Factors: Petitioner argued against discretionary denial under the Becton Dickinson factors because the prior art references asserted in the petition (Koyanagi, Alexander, Bertin, and Cooke) and the specific combinations were never presented to or considered by the Examiner during the original prosecution. Therefore, the petition raised new issues material to patentability.
  • §314(a) Fintiv Factors: Petitioner contended that denial under Fintiv would be inappropriate. The parallel district court litigation was in its early stages, with a claim construction hearing scheduled several months after the anticipated institution decision date and summary judgment motions even later. Petitioner argued that the PTAB proceeding would be an efficient alternative to litigation and significant court resources had not yet been expended on the invalidity issues.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1, 4, 5, 8, 10, 13-15 of the ’951 patent as unpatentable.