PTAB

IPR2020-01315

Advanced Micro Devices Inc v. Monterey Research LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Output Driver Circuit with Variable Current Supply
  • Brief Description: The ’455 patent discloses a buffer circuit featuring variable and selectable current sources designed to control the rise and fall times of an output signal. The technology aims to maintain performance across a range of operating voltages by adjusting a drive current, which in turn controls the switching speed of pull-up and pull-down transistors.

3. Grounds for Unpatentability

Ground 1: Claims 7, 8, 10, and 13 are obvious over Ozguc

  • Prior Art Relied Upon: Ozguc (Patent 6,037,811).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Ozguc, which discloses an output buffer with current-controlled rise and fall times, teaches every limitation of independent claim 7. Ozguc’s “first adjustable current source” was alleged to be the claimed “selectable current source,” as it generates a variable drive current (I1) to control a first driver transistor (MP1). Petitioner asserted that Ozguc’s adjustable source is selectable because it comprises a current mirror with multiple parallel current legs (Master, Center, Up, Down) that can be selectively enabled via drive signals (“DNB” and “UP”) to adjust the total drive current and, consequently, the output’s rise time.
    • Key Aspects: Petitioner contended that Ozguc’s structure of parallel current paths, where the “Up” and “Down” legs can be switched on or off, directly corresponds to the ’455 patent's concept of a "selectable current source" with "selectable current legs." The arguments for dependent claims 8, 10, and 13 followed from mappings of Ozguc's current leg switches and control logic.

Ground 2: Claims 7, 8, and 10-13 are obvious over Ozguc and Huber

  • Prior Art Relied Upon: Ozguc (Patent 6,037,811) and Huber (Patent 7,170,324).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground asserted that to the extent Ozguc alone does not render the claims obvious, the combination with Huber does. Petitioner argued Ozguc teaches the core buffer circuit with a selectable current source, while Huber teaches an efficient switching mechanism to improve its performance. Specifically, this combination addressed claim 11, which adds a second driver transistor and specific switching element configurations.
    • Motivation to Combine: Petitioner argued a person of ordinary skill in the art (POSITA) would combine Huber with Ozguc to improve performance and power efficiency. Ozguc’s switching mechanism was described as having a “shut-off delay” that leads to power waste and potential interference between pull-up and pull-down operations. Huber was presented as explicitly teaching a fast-acting switch (M4) to quickly shut off pull-up current when not needed, solving the very problem a POSITA would identify in Ozguc.
    • Expectation of Success: Success would be expected because the combination represented the application of a known technique (Huber's efficient shut-off switch) to a similar, known circuit (Ozguc's buffer circuit) to achieve a predictable improvement in performance.

Ground 3: Claims 1-6 and 14 are obvious over Ozguc, Huber, and Wu

  • Prior Art Relied Upon: Ozguc (Patent 6,037,811), Huber (Patent 7,170,324), and Wu (Patent 5,994,945).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground addressed independent claim 1 and its dependents. Petitioner asserted the combination of Ozguc and Huber taught a buffer circuit with variable pull-up and pull-down current supplies and efficient switching, as argued in other grounds. Wu was added to teach the key limitation of claim 1[b]: a variable current supply that generates a current "having at least one component that is inversely proportional to a power supply voltage." Petitioner argued Wu discloses a "current compensation circuit" for I/O buffers that generates a stable current with a component (IC) that is explicitly designed to be inversely proportional to the supply voltage (VCC), thereby compensating for voltage fluctuations.
    • Motivation to Combine: A POSITA, having already combined Ozguc and Huber for performance, would have been motivated to incorporate Wu’s teachings to address performance instability caused by variations in supply voltage and temperature—a well-known problem that Ozguc does not address. Wu’s compensation circuit was designed for the exact purpose of stabilizing currents in I/O buffers like Ozguc’s.
    • Expectation of Success: The combination was argued to be a predictable integration of complementary solutions. A POSITA would have reasonably expected to successfully use Wu's compensation circuit as the input for Ozguc's adjustable current source to create a buffer that is not only fast and efficient (per Huber) but also stable across different operating conditions.

  • Additional Grounds: Petitioner asserted additional obviousness challenges, including that claim 9 is obvious over Ozguc and Wu (Ground 4) and over Ozguc, Huber, and Wu (Ground 5). Petitioner also asserted that claims 11 and 12 are anticipated by or obvious over Huber alone (Grounds 6 and 7).

4. Relief Requested

  • Petitioner requested institution of an inter partes review (IPR) and cancellation of claims 1-14 of Patent 8,373,455 as unpatentable.