Analog Devices Inc v. Xilinx Inc

1. Case Identification

• Case #: IPR2020-01531
• Patent #: 8,548,071
• Filed: August 31, 2020
• Petitioner(s): Analog Devices, Inc.
• Patent Owner(s): Xilinx, Inc.
• Challenged Claims: 1-3, 7-9, and 12-19

2. Patent Overview

• Title: Integrated Circuit Enabling the Communication of Data and a Method of Communicating Data in an Integrated Circuit
• Brief Description: The ’071 patent discloses an integrated circuit containing a plurality of analog-to-digital converter (ADC) circuits. The system uses "programmable interconnect circuits" to select and configure a desired number of these ADCs to work in a time-interleaved manner, allowing a user to achieve a specific data conversion rate for a given application.

3. Grounds for Unpatentability

Ground I: Anticipation over Xia - Claims 1-3, 7-9, and 12-19 are anticipated by Xia

• Prior Art Relied Upon: Xia, B. et al., “A 10-bit 44-MS/s 20-mW Configurable Time-Interleaved Pipeline ADC for a Dual-Mode 802.11b/Bluetooth Receiver,” IEEE Journal of Solid-State Circuits (Mar. 2006) (“Xia”).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Xia, published over five years before the ’071 patent’s priority date, discloses every element of the challenged claims. Xia describes a configurable, time-interleaved ADC within a single integrated circuit for multi-standard wireless radios. For independent claims 1 and 7, Xia teaches an integrated circuit with an input port, a plurality of ADC circuits, and programmable interconnects (termed "programmable analog baseband" circuits) that enable a selectable connection between the input and the ADCs. For method claim 14, Xia teaches implementing multiple ADCs on the circuit, coupling an analog signal to it, and sampling that signal with the plurality of ADCs. Dependent claims were also argued to be disclosed, such as using different clock signals for each ADC (claim 3) and selecting the number of ADCs based on a desired sample rate (claim 16).

Ground II: Anticipation over Iwata - Claims 1, 3, 7-9, and 12-19 are anticipated by Iwata

• Prior Art Relied Upon: Japanese Patent Publication No. JP2004201026A to Iwata et al. (“Iwata”).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that Iwata, published seven years before the ’071 patent’s priority date, also anticipates all challenged claims. Iwata discloses a highly versatile, programmable A/D converter on a single integrated circuit capable of changing its resolution and conversion speed. It explicitly teaches using "switch groups" (the equivalent of programmable interconnect circuits) to programmatically select the number of "sequential conversion circuits" (ADCs) that sample an analog input signal. Petitioner contended that Iwata’s switch groups, which control the signal path from input channels to the ADCs, perform the exact function of the claimed programmable interconnects. The reference was argued to disclose all elements of independent claims 1, 7, and 14, including the input port, plurality of ADCs, programmable interconnects, and a clock generator that provides different, phase-shifted clock signals for time-interleaved operation.

Ground III: Obviousness over Iwata in view of Hsueh - Claim 2 is obvious over Iwata in view of Hsueh

• Prior Art Relied Upon: Iwata (Japanese Patent Publication No. JP2004201026A) and Hsueh (Patent 6,608,580).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground specifically addressed claim 2, which depends from claim 1 and adds the limitation that the input/output port comprises "a pair of input/output pins receiving a differential analog input signal." Petitioner argued that while Iwata discloses the base circuit of claim 1, it does not explicitly disclose a differential input. Hsueh was introduced because it teaches a "Differential Analog-to-Digital Converter" of the same type used in Iwata (successive approximation ADC) and explicitly discloses receiving differential signals (Vin+ and Vin-) to improve performance and reduce errors.
  • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would have been motivated to modify Iwata’s programmable architecture to incorporate the differential ADC inputs taught by Hsueh. Hsueh explained that differential ADCs "address [the] shortcoming" of traditional ADCs being prone to errors. Therefore, a POSITA would have recognized the clear benefit of improving the noise immunity and accuracy of Iwata's versatile converter by implementing a well-known differential signaling scheme.
  • Expectation of Success: Petitioner argued that adapting a single-ended circuit to operate differentially was a routine design choice and a predictable modification for a POSITA at the time. The modification would have yielded the expected benefits of improved performance with no undue experimentation.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial of institution under 35 U.S.C. §314(a) based on Fintiv factors was not appropriate. The co-pending district court litigation was before a judge who typically stays cases when a corresponding inter partes review (IPR) is instituted. Furthermore, the district court trial was scheduled for a date after a Final Written Decision (FWD) in the IPR would be due, weighing against denial.

5. Relief Requested

• Petitioner requested institution of an IPR and cancellation of claims 1-3, 7-9, and 12-19 of the ’071 patent as unpatentable.