Apple Inc v. Solas OLED Ltd

1. Case Identification

• Case #: IPR2020-01546
• Patent #: 7,573,068
• Filed: September 11, 2020
• Petitioner(s): Apple Inc.
• Patent Owner(s): Solas OLED Ltd.
• Challenged Claims: 1, 5, 6, 8-13, and 17

2. Patent Overview

• Title: Transistor Array Substrate and Display Panel
• Brief Description: The ’068 patent discloses a circuit arrangement and manufacturing method for organic electroluminescent (EL) display panels. The invention addresses high electrical resistance and voltage drops in conventional thin-film supply lines by incorporating thick "feed interconnections" fabricated on a different layer, which connect to the thin-film supply lines to improve power delivery across the display.

3. Grounds for Unpatentability

Ground 1: Claims 1, 5, 6, 8-13, and 17 are obvious over Shirasaki in view of Childs.

• Prior Art Relied Upon: Shirasaki (International Publication No. WO 03/058328) and Childs (Patent 7,358,529).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Shirasaki discloses a display panel with a pixel circuit arrangement and driving method that is nearly identical to that of the ’068 patent, including a three-transistor layout. However, Shirasaki’s design utilizes conventional thin-film supply lines, which were known to suffer from performance issues like voltage drop due to high resistance. Petitioner contended that Childs directly addresses this widely recognized problem in the same field of active matrix displays. Childs teaches using thick, low-resistance "conductive barriers" fabricated over the thin-film supply lines to provide a supplemental, low-resistance current path. Petitioner asserted these conductive barriers are analogous to the ’068 patent’s claimed "feed interconnections."
  • Motivation to Combine: Petitioner argued a person of ordinary skill in the art (POSITA) would combine Childs's solution with Shirasaki's circuit design for the predictable purpose of solving the known voltage drop problem inherent in Shirasaki's thin-film supply lines. The combination was presented as a straightforward application of a known technique from Childs to improve a similar device in Shirasaki. The similar pixel layouts in both references, particularly the placement of supply lines between rows of pixels, would further motivate the combination to achieve benefits described in Childs, such as improved wiring and optical separation.
  • Expectation of Success: Petitioner asserted a POSITA would have had a high expectation of success. The addition of Childs’s conductive barriers over Shirasaki’s supply lines was described as a straightforward modification, as Shirasaki’s layout already placed the supply lines on the perimeters of the light-emitting areas, preventing interference. To further simplify fabrication, a POSITA would have found it obvious to swap the layers on which Shirasaki’s signal and supply lines were fabricated, a minor modification that would facilitate the connection between the new barriers and the existing supply lines.

4. Key Claim Construction Positions

Petitioner dedicated significant analysis to claim construction, arguing its unpatentability case is strong under both its proposed constructions and the broader constructions adopted in parallel litigation.

• "[formed on/connected to] said plurality of supply lines along said plurality of supply lines": Petitioner argued for a construction requiring the feed interconnections to be “stacked on or making multiple contacts with said plurality of supply lines over the length of each supply line.” Petitioner maintained that the proposed prior art combination met this construction as well as the broader construction of “over the length or direction of” adopted by a district court.
• "patterned together": Petitioner argued the correct construction requires the recited lines and transistor electrodes to be "formed on the same layer from the same process step." However, Petitioner asserted that the prior art combination also satisfies the broader construction of "patterned to fit together" adopted in co-pending litigation, making it unnecessary for the Board to resolve the dispute.
• "feed interconnections": Petitioner adopted the construction agreed upon in parallel litigation: “conductive structures in a different layer or layers than the supply line that also provide connections to a source that supplies voltage and/or current.”

5. Arguments Regarding Discretionary Denial

Petitioner presented extensive arguments that discretionary denial under either §314(a) or §325(d) would be inappropriate, focusing on both the General Plastics and Fintiv factors.

• General Plastics Factors: Petitioner argued against denial based on serial petitions, emphasizing that this was its first inter partes review (IPR) petition against the ’068 patent. Petitioner stated it has no significant relationship with the petitioner in a prior IPR (IPR2020-01238, filed by LG Display) and that its petition relies on a different primary reference (Shirasaki) than the prior IPR.
• Fintiv Factors: Petitioner argued against denial based on parallel district court litigation for several reasons:
  • The parallel litigation was in its early stages, with claim construction having just concluded and dispositive motions not due for many months.
  • The scheduled trial date was uncertain and likely to be delayed, weighing in favor of institution.
  • Petitioner stipulated that, if the IPR is instituted, it would not pursue the same invalidity grounds in the district court litigation, eliminating concerns of overlapping issues.
  • The merits of the petition are exceptionally strong, and the primary prior art references (Shirasaki and Childs) were never considered during the original prosecution of the ’068 patent.

6. Relief Requested

• Petitioner requested the institution of an inter partes review and the cancellation of claims 1, 5, 6, 8-13, and 17 of Patent 7,573,068 as unpatentable.