PTAB

IPR2020-01561

Xilinx Inc v. Analog Devices Inc

Log In
Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Analog-to-Digital Converter System
  • Brief Description: The ’452 patent discloses an analog-to-digital converter (ADC) system that improves linearity by injecting a random analog dither signal into the analog input signal. The combined signal is processed through a pipeline of converter stages, and the digital representation of the dither signal is subsequently subtracted from the final digital output code.

3. Grounds for Unpatentability

Ground A: Claims 1-2, 8-9, and 13-16 are obvious over Cesura.

  • Prior Art Relied Upon: Cesura (Patent 6,970,125).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Cesura discloses all limitations of independent claims 1 and 13. Cesura teaches a pipelined ADC system with a sampler (S/H amplifier 110) and successive converter stages (1053-1050). It injects analog dither signals ("t") from a pseudo-random number generator (PRN 205) via a digital-to-analog converter (DAC 210) into the first converter stage. Cesura further discloses an aligner/corrector (shifter 203) that creates a combined digital code and a decoder (amplifiers 225/230 and logic 240) that creates a value corresponding to the dither signal, which is then differenced (adder 235) from the combined code to produce the final system output.
    • Motivation to Combine: Not applicable as this ground relies on a single reference. Petitioner asserted that Cesura’s own disclosure renders the claimed invention obvious.
    • Expectation of Success: Not applicable for a single-reference ground. Petitioner contended that implementing the claimed system based on Cesura's teachings would have been straightforward for a person of ordinary skill in the art (POSITA).

Ground B: Claims 12, 19, and 20 are obvious over Cesura in view of Lewis and Bjornsen.

  • Prior Art Relied Upon: Cesura (Patent 6,970,125), Lewis ("A Pipelined 5-Msample/s 9-bit Analog-to-Digital Converter," IEEE Journal of Solid-State Circuits, 1987), and Bjornsen (Patent 7,129,874).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon Ground A, arguing that while Cesura teaches the high-level functional system for dither injection, it omits specific circuit-level details. Claims 12, 19, and 20 recite specific implementations using first and second dither capacitors. Petitioner contended that Lewis discloses the standard switched-capacitor circuitry for implementing pipelined ADC stages, which Cesura illustrates only functionally. Bjornsen was argued to teach the specific use of dither capacitors (98) switchably connected to different voltage levels to inject dither signals into a switched-capacitor circuit.
    • Motivation to Combine: A POSITA, seeking to implement the functional ADC system taught by Cesura, would have been motivated to "fill in the blanks" of Cesura's high-level schematic. The POSITA would naturally look to well-known references like Lewis for standard pipelined stage circuit architecture and to Bjornsen for a known method of injecting dither signals into such a circuit using dither capacitors.
    • Expectation of Success: A POSITA would have a reasonable expectation of success because combining the references involved applying known techniques (Bjornsen's dither injection) to a standard, compatible architecture (Lewis's pipeline stage) to implement a known function (Cesura's dithered ADC), yielding predictable results.

Ground C: Claims 1-4, 8, 9, and 13-16 are obvious over Fu in view of Lewis.

  • Prior Art Relied Upon: Fu ("A Digital Background Calibration Technique for Time-Interleaved Analog-to-Digital Converters," IEEE Journal of Solid-State Circuits, 1998) and Lewis (the 1987 IEEE Journal article).

  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner argued that Fu, like Cesura, discloses a complete high-level pipelined ADC system that meets the limitations of the independent claims. Fu teaches injecting dither signals from a random number generator (RNG) via a DAC for background calibration, processing the combined signal through successive stages, and digitally removing the dither component using a decoder (gain stage G1) and differencer. Similar to the argument in Ground B, Petitioner contended that Fu discloses these elements functionally without providing specific circuit details. Lewis was cited as providing the conventional switched-capacitor circuit implementation for the sampler ("SHA") and converter stages that Fu omits.
    • Motivation to Combine: The motivation was again presented as implementing a functionally-disclosed system with known circuit components. A POSITA reading Fu's disclosure of a pipelined ADC would be motivated to use the well-understood switched-capacitor circuits taught by Lewis to build Fu's functional blocks, as this represented a standard and common practice in the field.
    • Expectation of Success: Success would be expected as it involved the application of a standard circuit design (Lewis) to implement a functionally described system (Fu), a routine task for a skilled artisan.

  • Additional Grounds: Petitioner asserted an additional obviousness challenge (Ground D) for claims 12, 19, and 20 based on the combination of Fu, Lewis, and Bjornsen, relying on similar design modification theories as presented in Ground B.

4. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under Fintiv would be inappropriate. The petition was filed expeditiously, just two weeks after receiving infringement contentions. The parallel district court trial date was over 18 months away, placing it well after the statutory deadline for a Final Written Decision, and Petitioner stated its intent to seek a stay upon institution. Petitioner further argued that other factors, such as the complexity of the technology and the fact that eight patents are asserted in the parallel litigation, make the Patent Trial and Appeal Board an efficient and more appropriate forum for resolving the invalidity issues.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-4, 8-9, 12-16, and 19-20 of the ’452 patent as unpatentable.