Xilinx Inc v. Arbor Global Strategies LLC

1. Case Identification

• Case #: IPR2020-01568
• Patent #: 7,282,951
• Filed: September 4, 2020
• Petitioner(s): Xilinx, Inc.
• Patent Owner(s): Arbor Global Strategies LLC
• Challenged Claims: 1-2, 4-6, 8-29

2. Patent Overview

• Title: Reconfigurable Processor Module Comprising Hybrid Stacked Integrated Circuit Die Elements
• Brief Description: The ’951 patent describes a processor module created by stacking thinned integrated circuit die elements, such as a microprocessor, memory, and/or a field-programmable gate array (FPGA). The stacked die are interconnected using electrical contacts that traverse the thickness of the individual die.

3. Grounds for Unpatentability

Ground 1: Obviousness over Zavracky, Chiricescu, and Akasaka - Claims 1-2, 4-6, 8-24, 27, and 29 are obvious over Zavracky in view of Chiricescu and Akasaka.

• Prior Art Relied Upon: Zavracky (Patent 5,656,548), Chiricescu (a 1998 IEEE article), and Akasaka (a 1986 IEEE article).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that the base reference, Zavracky, disclosed the core concept of a processor module with vertically stacked and interconnected circuit elements, including programmable logic devices, memory, and microprocessors. Chiricescu, which explicitly builds upon Zavracky’s technology from the same university research group, was asserted to teach using a stacked memory with an FPGA to accelerate FPGA reconfiguration. To meet the limitation of contact points distributed throughout the die surfaces, Petitioner relied on Akasaka, which taught 3D integrated circuits with "several thousands or several tens of thousands of via holes" distributed across the die surface to shorten interconnections and improve signal processing speeds. Together, this combination was alleged to teach a processor module with stacked FPGA and memory elements connected by distributed through-die contacts.
  • Motivation to Combine: A POSITA would combine Zavracky and Chiricescu because Chiricescu expressly used Zavracky's 3D stacking principles to solve the known problem of high FPGA configuration time, promising a "significant improvement." A POSITA would have been further motivated to incorporate Akasaka's teaching of high-density, distributed via holes to increase bandwidth and processing speed in the Zavracky/Chiricescu stack, an advantage suggested by Akasaka itself for parallel processing applications.
  • Expectation of Success: Petitioner contended a POSITA would have had a high expectation of success, as the combination involved applying known techniques (high-density vias) to a known architecture (stacked dies) to achieve predictable benefits (improved speed and reconfigurability).

Ground 2: Obviousness over Zavracky, Chiricescu, Akasaka, and Trimberger - Claim 25 is obvious over the combination of Ground 1 in view of Trimberger.

• Prior Art Relied Upon: Zavracky, Chiricescu, Akasaka, and Trimberger (a 1997 IEEE article).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground added Trimberger to address the additional limitation of claim 25, which required the memory array to be "functional as block memory for said processing element." Petitioner asserted that Trimberger taught a time-multiplexed FPGA where on-chip memory is "accessible as block RAM for applications" running on the FPGA, allowing it to be used efficiently as a large block of memory.
  • Motivation to Combine: A POSITA would have sought to incorporate Trimberger’s teaching into the base combination to support FPGA applications that require fast, local memory. Using a stacked memory die as a dedicated block memory was argued to be a cost- and silicon-efficient design choice for handling specific tasks, compared to consuming limited FPGA logic space.

Ground 3: Obviousness over Zavracky, Chiricescu, Akasaka, and Satoh - Claim 26 is obvious over the combination of Ground 1 in view of Satoh.

• Prior Art Relied Upon: Zavracky, Chiricescu, Akasaka, and Satoh (WO 00/62339).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground added Satoh to address claim 26’s limitation that the contact points are "functional to provide test stimulus" from the FPGA to another element. Satoh was presented as teaching the use of a variable logic circuit (FPGA) to generate and supply test signals to memory circuits on the same chip.
  • Motivation to Combine: Petitioner argued that stacking multiple functional dies, as taught in the base combination, inherently increased the risk of manufacturing defects and module failure. A POSITA would have been motivated to integrate Satoh's method to test the co-stacked memory using the FPGA. This approach would provide rigorous testing, improve manufacturing yield, and avoid the cost and complexity of a separate, dedicated test chip.

Ground 4: Obviousness over Zavracky, Chiricescu, Akasaka, and Alexander - Claim 28 is obvious over the combination of Ground 1 in view of Alexander.

• Prior Art Relied Upon: Zavracky, Chiricescu, Akasaka, and Alexander (a 1995 conference proceeding).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground added Alexander to address claim 28, which required that a third integrated circuit element include "another field programmable gate array." Alexander taught building a 3D FPGA by stacking multiple 2D FPGA dies and vertically interconnecting them with through-die vias.
  • Motivation to Combine: Zavracky disclosed that its stacked architectures were useful for "signal processing applications," which often require parallel processing. A POSITA would have recognized that for such applications, implementing Alexander’s stacked FPGA architecture would be a powerful and preferable alternative to slower general-purpose microprocessors or inflexible custom hardware. This would involve simply adding another known die type (a second FPGA) to the existing 3D stack.

4. Arguments Regarding Discretionary Denial

• Petitioner argued against discretionary denial under both §325(d) and §314(a) (Fintiv). It asserted that the prior art combinations relied upon in the petition were not considered during prosecution and are not cumulative of the cited art.
• Regarding the Fintiv factors, Petitioner argued for institution, emphasizing that the co-pending district court litigation trial date (May 23, 2022) was scheduled for well after the projected date for a Final Written Decision (FWD) from the PTAB (March 2022). Petitioner further argued that the district court had not yet invested significant resources in claim construction or other substantive validity issues.
• As a key factor, Petitioner submitted a stipulation that, if the IPR is instituted, it would not pursue in the district court any invalidity ground that was raised or could have been reasonably raised in the IPR.

5. Relief Requested

• Petitioner requested the institution of an inter partes review and the cancellation of claims 1-2, 4-6, and 8-29 of the ’951 patent as unpatentable.