Xilinx Inc v. Arbor Global Strategies LLC

1. Case Identification

• Case #: IPR2020-01570
• Patent #: RE42,035
• Filed: September 4, 2020
• Petitioner(s): Xilinx, Inc.
• Patent Owner(s): Jon M. Huppenthal
• Challenged Claims: 1-38

2. Patent Overview

• Title: Reconfigurable Processor Module Comprising Hybrid Stacked Integrated Circuit Die Elements
• Brief Description: The ’035 patent describes a reconfigurable processor module created by stacking thinned integrated circuit die elements, such as a microprocessor, memory, and a field-programmable gate array (FPGA). The stacked dies are interconnected using contacts that traverse the thickness of each die element.

3. Grounds for Unpatentability

Ground 1: Obviousness over Zavracky, Chiricescu, and Akasaka (Claims 1-30, 33, 36, 38)

• Prior Art Relied Upon: Zavracky (Patent 5,656,548), Chiricescu (a 1998 IEEE article), and Akasaka (a 1986 IEEE article).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that the combination of these references taught all limitations of the challenged claims. Zavracky disclosed a method for forming a three-dimensional processor by vertically stacking and interconnecting circuit elements, including programmable logic devices, microprocessors, and memory. Chiricescu, which explicitly cited Zavracky’s underlying application, taught a 3-D FPGA with an integrated memory layer to accelerate reconfiguration time, a known problem with FPGAs. Akasaka taught using tens of thousands of "via holes" distributed across the surface of stacked dies to permit high-speed parallel processing and improve system performance. Petitioner asserted this combination disclosed a processor module with stacked die elements (Zavracky), including an FPGA and memory (Chiricescu), electrically coupled by distributed contact points that traverse the die thickness (Zavracky, Akasaka).
  • Motivation to Combine: A POSITA would combine Zavracky and Chiricescu because Chiricescu (from the same university research group) explicitly built upon Zavracky’s technology to solve the well-known problem of high FPGA configuration times. A POSITA would be further motivated to incorporate Akasaka's teaching of distributed via holes into the Zavracky/Chiricescu stack to achieve the predictable advantages of increased bandwidth, connectivity, and parallel processing speed, benefits that both Akasaka and Zavracky suggested.
  • Expectation of Success: A POSITA would have had a reasonable expectation of success because the combination involved integrating technologies from a related research effort (Zavracky and Chiricescu) and applying a well-understood, advantageous interconnection technique (Akasaka) to yield predictable improvements in performance.

Ground 2: Obviousness over Zavracky, Chiricescu, Akasaka, and Trimberger (Claims 31, 32, 34)

• Prior Art Relied Upon: Zavracky (Patent 5,656,548), Chiricescu (a 1998 IEEE article), Akasaka (a 1986 IEEE article), and Trimberger (a 1997 IEEE article).

• Core Argument for this Ground:

  • Prior Art Mapping: This ground built upon the core combination of Zavracky, Chiricescu, and Akasaka and added Trimberger to teach the specific limitation that the memory array is functional as "block memory" for the FPGA processing element. Trimberger taught a time-multiplexed FPGA where co-located memory is accessible as "block RAM" for applications running on the FPGA, allowing it to be used more efficiently.
  • Motivation to Combine: Petitioner argued that a POSITA, seeking to support FPGA applications requiring fast local memory in the Zavracky/Chiricescu/Akasaka 3D stack, would have been motivated to incorporate Trimberger’s teaching. Using a separate, dedicated block memory was a known, silicon-efficient method to augment FPGAs, which have limited programmable logic space. Combining this known design principle with a stacked architecture would predictably improve memory options for the FPGA.
  • Expectation of Success: A POSITA would have expected success in applying Trimberger's teachings, as it represented the application of a known engineering design principle (using block memory with an FPGA) to a known architecture (a 3D stack) to achieve the predictable result of improved performance.

• Additional Grounds: Petitioner asserted additional obviousness challenges based on the core Zavracky/Chiricescu/Akasaka combination plus a single additional reference for specific claims. These included adding Satoh (WO 00/62339) for its teachings on using an FPGA to provide test stimulus to memory (Claim 35), and adding Alexander (a 1995 conference proceeding) for its teachings on stacking multiple FPGA dies for parallel processing applications (Claim 37).

4. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial would be inappropriate. Under 35 U.S.C. §325(d), Petitioner asserted that the prior art combinations presented were not considered by the USPTO during prosecution. Petitioner also argued that the General Plastic and Fintiv factors weighed strongly in favor of institution.
• Key Fintiv arguments included that the co-pending district court trial was scheduled for May 2022, months after the projected Final Written Decision date, and that Petitioner stipulated it would not pursue the same grounds in district court if the IPR was instituted, removing the possibility of parallel litigation on overlapping issues.

5. Relief Requested

• Petitioner requests institution of inter partes review and cancellation of claims 1-38 of the ’035 patent as unpatentable.