Analog Devices Inc v. Xilinx Inc

1. Case Identification

• Case #: IPR2020-01596
• Patent #: 7,187,709
• Filed: September 14, 2020
• Petitioner(s): Analog Devices, Inc.
• Patent Owner(s): Xilinx, Inc.
• Challenged Claims: 1-17

2. Patent Overview

• Title: High Speed Configurable Transceiver Architecture
• Brief Description: The ’709 patent describes an integrated circuit (IC) featuring a programmable fabric, a processor core surrounded by the fabric, and multiple configurable transceivers at the fabric's periphery. The core invention asserted during prosecution was the ability to configure the transceivers’ serializers and deserializers to transmit and receive data at the same selected bit rate.

3. Grounds for Unpatentability

Ground 1: Obviousness of Claims 1-5, 8-12, and 15-17 over OneChip, ORT8850, and Bursky

• Prior Art Relied Upon: OneChip (a 1996 IEEE paper), ORT8850 (a Sept. 2000 datasheet from Lucent Technologies), and Bursky (an Oct. 2000 article in Electronic Design).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that OneChip taught the foundational system-on-a-chip (SoC) architecture of the ’709 patent, including a fixed-logic processor core surrounded by a "sea of programmable logic" (i.e., programmable fabric) with peripheral I/O pads. ORT8850 was presented as disclosing the specific configurable transceiver technology, including serializers and deserializers (SERDES) that could be configured to operate at multiple, selectable bit rates (e.g., 850, 424, or 212 Mbits/s) and were designed for integration into Field-Programmable System Chips (FPSCs).
  • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine ORT8850’s well-documented configurable transceivers with OneChip’s SoC architecture. The motivation was to improve the I/O capabilities of the SoC with a flexible, high-speed data communication interface, which was a predictable step in the known industry trend of increasing on-chip integration to leverage greater transistor density. Bursky was cited as secondary evidence confirming this trend, explicitly teaching the combination of high-speed programmable-logic with dedicated, on-chip, configurable SERDES blocks to meet market demands for more flexible solutions.
  • Expectation of Success: A POSITA would have had a reasonable expectation of success because combining these elements involved applying a known technique (configurable SERDES) to a known platform (SoC with programmable logic) to achieve a predictable improvement in performance and flexibility. Both primary references originate from the same field of endeavor.

Ground 2: Obviousness of Claims 1-5, 8-12, and 15-17 over Chan, ORT8850, and OneChip

• Prior Art Relied Upon: Chan (Patent 6,542,096), ORT8850 (a Sept. 2000 datasheet), and OneChip (a 1996 IEEE paper).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner asserted that Chan disclosed the very architecture claimed in the ’709 patent: a single programmable IC with a programmable fabric, an embedded circuit (processor core), and configurable SERDES transceivers located at the periphery. ORT8850 was used to supply the more detailed teachings for specific transceiver features required by the claims, such as selectable bit rates for both the serializer and deserializer, support for protocols like Fibre Channel and SONET, and the presence of components like a loss-of-synchronization detector, CRC generator, and elastic buffers.
  • Motivation to Combine: The motivation was to implement the specific, well-understood, and commercially desirable transceiver features detailed in ORT8850 into the nearly identical SoC architecture already disclosed by Chan. This combination represented the integration of known functional blocks to enhance an existing platform. OneChip was used as background art to further demonstrate that the processor-surrounded-by-fabric layout was a well-established design paradigm, reinforcing the obviousness of Chan’s architecture.
  • Expectation of Success: Since Chan already taught the fundamental integration of SERDES into a programmable device, a POSITA would have found it straightforward and predictable to implement the more advanced, but standard, features of a known transceiver block like ORT8850.

• Additional Grounds: Petitioner asserted additional obviousness challenges (Grounds 3 and 4) against claims 1-3, 6-8, 10, 13-14, and 17. These grounds relied on the same core combinations of OneChip/ORT8850 and Chan/ORT8850, but added QL80FC (an Aug. 2000 datasheet from QuickLogic) to provide more explicit supplemental teachings for certain transceiver features, particularly those related to the Fibre Channel protocol, such as CRC generation/checking and loss-of-synchronization state machines.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under 35 U.S.C. §314(a) and the Fintiv factors was not appropriate. The core reasons provided were that the judge in the co-pending litigation (D. Del.) typically grants stays pending IPR, the scheduled trial date was after the statutory deadline for a Final Written Decision (FWD), and the IPR challenges claims that are not asserted in the parallel litigation, weighing against denial.

5. Relief Requested

• Petitioner requests the institution of an inter partes review and the cancellation of claims 1-17 of the ’709 patent as unpatentable under 35 U.S.C. §103.