PTAB

IPR2020-01625

Analog Devices Inc v. Xilinx Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Programmable Serializing Data Path
  • Brief Description: The ’251 patent discloses a programmable serializing data path capable of converting parallel data of varying widths into a serial bit stream. The system is specifically designed to accommodate different communication protocols by handling parallel data words that are multiples of 8 bits (e.g., for SONET) or multiples of 10 bits (e.g., for 10G Ethernet) within a single, non-redundant circuit.

3. Grounds for Unpatentability

Ground 1: Anticipation of Claims 1-4 under §102 by Measor

  • Prior Art Relied Upon: Measor (Application # 2001/0007577).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Measor, published over two years before the ’251 patent’s effective filing date, discloses every limitation of claims 1-4. Measor teaches a programmable serializer that converts parallel data of different widths (16-bit and 20-bit) into serial data using a single circuit structure. This structure includes a three-stage multiplexer (mux) tree and a programmable timing circuit (a ring counter) that generates a multiple-state control sequence based on a data width selection input (“Select 16 or 20”). Petitioner asserted that Measor’s control sequence for selecting 4-bit nibbles from the parallel data is functionally identical to that disclosed in the ’251 patent.
    • Key Aspects: The core of the argument rested on the striking similarity between Measor’s serializer architecture (Figure 3) and the preferred embodiment of the ’251 patent (Figure 4), both addressing the same problem of multi-protocol serialization.

Ground 2: Obviousness of Claims 1-4, 7-10, and 13-16 under §103 over Measor in view of Xcell Journal

  • Prior Art Relied Upon: Measor (Application # 2001/0007577) and Xcell Journal (a Spring 2002 publication by Xilinx).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner contended that to the extent Measor does not anticipate every limitation, the combination with Xcell renders the claims obvious. Xcell described a Xilinx Virtex-II Pro FPGA with high-speed transceivers that included a "Serializer" block, but it did not disclose the internal circuitry. Measor provided a detailed, well-understood mux-tree implementation for a multi-protocol serializer. The combination supplied the apparatus limitations of claims 7 and 13, as Xcell’s FPGA explicitly included processing modules (IBM PowerPC processors), memory, and software macros (the "Aurora core") to control the transceivers. Xcell also taught a full-rate clocking scheme, which would make it obvious to modify Measor’s half-rate clock if desired.
    • Motivation to Combine: A POSITA would combine the references to implement the functional "Serializer" block in Xcell’s FPGA with a known, power-efficient, and proven circuit design like that of Measor. Both references were in the same field of high-speed communication in FPGAs and addressed the same need to support protocols like SONET and Ethernet.
    • Expectation of Success: Success would be predictable, as it involved applying a known serializing technique (Measor) to a known FPGA device (Xcell) that required such functionality. The components in Measor were standard and readily adaptable.

Ground 3: Obviousness of Claims 1-4, 7-10, and 13-16 under §103 over ORT8850 in combination with Measor

  • Prior Art Relied Upon: ORT8850 (a September 2000 data sheet from Lucent) and Measor (Application # 2001/0007577).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground presented an alternative to Ground 2. The ORT8850 data sheet described a Field-Programmable System Chip (FPSC) with configurable transceivers for various protocols, including SONET and Gigabit Ethernet. Like Xcell, it disclosed a functional "Mux Parallel to Serial" block without implementation details. The combination with Measor’s detailed circuit provided all limitations. ORT8850 explicitly taught support for selectable data rates and software control via an embedded microprocessor soft-core, directly teaching the "processing module" and "memory" elements of apparatus claims 7 and 13.
    • Motivation to Combine: A POSITA would be motivated to fill the implementation gap in the ORT8850’s serializer with the specific, functional, and well-documented circuit from Measor. ORT8850 was designed for multiple protocols with varying data widths (multiples of 8 or 10), creating a clear need for a flexible serializer solution exactly like the one Measor provided.
    • Expectation of Success: The combination was a predictable pairing of a system needing a specific function with a known circuit providing that exact function, resulting in a serializer capable of handling multiple data widths and rates as intended by both references.

4. Key Claim Construction Positions

  • Petitioner argued that several terms reciting a "module" are nonce words used in a purely functional manner and should be construed as means-plus-function limitations under 35 U.S.C. §112, para. 6.
  • For example, the "processing module" of claims 7 and 13 was argued to be a means-plus-function term.
    • Claimed Function: To receive parallel data, obtain its data width (of a first or second multiple), obtain a desired serial data rate, generate a multiple state control sequence based on the width and rate, and convert the parallel data to serial data using that sequence.
    • Corresponding Structure: Petitioner identified the corresponding structure in the ’251 patent’s Figure 4 as the parallel-to-serial converter (84) combined with the programmable timing circuit (82).

5. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under Fintiv was not appropriate. The co-pending district court litigation was before a judge who typically grants stays pending IPR. Furthermore, the trial was scheduled for a date after a Final Written Decision would issue, and the petition challenged claims that were not at issue in the litigation, weighing against denial.

6. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1-4, 7-10, and 13-16 of the ’251 patent as unpatentable under 35 U.S.C. §§ 102 and 103.