Qualcomm Inc v. Monterey Research LLC

1. Case Identification

• Case #: IPR2021-00121
• Patent #: 7,977,797
• Filed: October 26, 2020
• Petitioner(s): Qualcomm Incorporated
• Patent Owner(s): Monterey Research LLC
• Challenged Claims: 1-12 and 14-15

2. Patent Overview

• Title: Semiconductor Device with Multiple Etch Stop Insulation Layer and Method of Fabrication
• Brief Description: The ’797 patent discloses integrated circuit structures and fabrication processes for forming a dual damascene contact region. The invention uses a multiple etch stop insulation layer and a non-lithography spacer formation process to create a contact structure where the bottom opening (substrate coupling area) is smaller than the top opening (metal layer coupling area), aiming to improve process control and increase device density.

3. Grounds for Unpatentability

Ground 1: Claims 1-8 are obvious over Peng in view of Brase

• Prior Art Relied Upon: Peng (Patent 7,338,903) and Brase (Patent 6,576,550).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Peng discloses a dual damascene process with the same sequence of layers as the ’797 patent’s claimed "multiple etch stop insulation layer." Peng shows a first barrier layer (claimed first etch stop), a first dielectric layer, a second etch stop layer, and a second dielectric layer. Peng also optionally discloses sidewall protecting layers that function as the claimed spacer regions, resulting in a contact structure with a wider top and narrower bottom. Brase was argued to supply the context of a complete integrated circuit, disclosing standard structures like transistors with source/drain regions in a substrate, which would surround Peng’s dual damascene contact.
  • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would have been motivated to implement Peng's damascene structure within the well-known integrated circuit context shown by Brase to create a complete, functional device. Petitioner asserted that Peng’s disclosure is agnostic to the specific contents of the substrate and is explicitly intended for use in integrated circuit products, making the combination straightforward and logical.
  • Expectation of Success: A POSITA would have a reasonable expectation of success as both references describe standard dual damascene processes and components used in semiconductor manufacturing, presenting no technical challenges to their combination.

Ground 2: Claims 1-8 and 11-12 are obvious over Peng and Brase in view of Chien

• Prior Art Relied Upon: Peng (Patent 7,338,903), Brase (Patent 6,576,550), and Chien (Patent 6,365,504).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground builds on Ground 1 by introducing Chien. While Peng discloses optional sidewall layers, Petitioner argued Chien explicitly teaches using spacers formed via a non-lithographic, anisotropic etch process to serve as an etch mask for the lower via hole in a dual damascene structure. This process directly maps to the ’797 patent’s "non-lithography spacer formation process" recited in claim 11. The resulting structure, like in Ground 1, has a contact bottom smaller than its top.
  • Motivation to Combine: A POSITA would combine Chien with Peng to gain the known benefits of using spacers as an etch mask. Chien explicitly states this technique solves common alignment problems between the trench and via masks, provides better control over the via’s critical dimension, and aids overall process control. These were known challenges in dual damascene fabrication that a POSITA would seek to solve.
  • Expectation of Success: The combination was asserted to be predictable because it involves applying a known process improvement (Chien's spacers) to a standard dual damascene structure (Peng's layer stack).

Ground 3: Claims 1-7 and 11 are obvious over Lin in view of Chien

• Prior Art Relied Upon: Lin (Application # 2004/0124420) and Chien (Patent 6,365,504).

• Core Argument for this Ground:

  • Prior Art Mapping: Petitioner presented Lin as an alternative primary reference to Peng. Lin was argued to disclose the same fundamental multi-layer stack for a dual damascene structure, including a first etch stop layer, a first low-k dielectric, a second etch stop layer, and a second low-k dielectric. Critically, Lin explicitly names the layers as "etch stop layers" and discloses forming a trench by etching through both the upper dielectric and the second etch stop layer. As in Ground 2, Chien was used to teach the formation of spacers via a non-lithographic process to define the via opening.
  • Motivation to Combine: The motivation to combine Lin and Chien was the same as for Peng and Chien: to use Chien's spacer-as-mask technique to improve alignment and process control in Lin's dual damascene structure. Petitioner noted Lin provides more explicit disclosure for certain elements, serving as a robust alternative to Peng.
  • Expectation of Success: Success would be expected as this ground again combines two known, compatible semiconductor processing techniques to achieve predictable benefits.

• Additional Grounds: Petitioner asserted additional obviousness challenges for claims 10 and 14 by adding Chen (Patent 6,570,257) to the combinations of Grounds 1, 2, and 3. Chen was argued to teach adding an anti-reflective coating (ARC) layer to improve dimensional control during photolithographic etching steps.

4. Key Claim Construction Positions

Petitioner argued for constructions of several key terms that were central to its invalidity arguments:

• “etch stop layer”: Argued to mean a layer with a significantly slower etching rate than a neighboring layer for a given etchant. This was a standard industry definition and key to identifying corresponding layers in the prior art.
• “a non-lithography spacer formation process”: Construed as a process for forming spacers without a lithographically-patterned photoresist layer, such as by depositing a conformal layer followed by an anisotropic etch. This was crucial for mapping Chien's process to claim 11.
• “a spacer region such that a substrate coupling area ... is smaller than a metal layer coupling area”: Petitioner argued the phrase "such that" requires the spacer region to control or cause the smaller substrate coupling area, for instance by acting as an etch mask. Petitioner contrasted this with the Patent Owner's apparent litigation construction, which Petitioner claimed would only require the spacer's presence alongside the size differential, without a causal link. This distinction was critical to Petitioner's argument that its combinations met the claims while overcoming the prosecution history.

5. Arguments Regarding Discretionary Denial

Petitioner argued that the grounds presented were not cumulative of the art considered during prosecution and that institution should not be denied under §325(d).

• Petitioner asserted that the primary references Peng, Lin, and Brase, as well as the secondary reference Chen, were never before the Examiner.
• While Chien was considered during prosecution of the parent ’727 patent, Petitioner argued it was applied differently. The Examiner previously rejected claims as anticipated by Chien, but the applicant overcame the rejection by adding limitations related to the dielectric layer structure, not by disputing Chien's disclosure of using spacers as an etch mask. Petitioner’s grounds rely on Peng or Lin for the layer structure and use Chien only for its undisputed teaching of spacer formation, a combination the Examiner never asserted.

6. Relief Requested

• Petitioner requests institution of IPR and cancellation of claims 1-12 and 14-15 of Patent 7,977,797 as unpatentable under 35 U.S.C. §103.