PTAB

IPR2021-00179

Google LLC v. Singular Computing LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Low Precision High Dynamic Range Processing Unit
  • Brief Description: The 8,407,273 patent describes a device with at least one "low precision high dynamic range" (LPHDR) execution unit. This unit performs mathematical operations, such as multiplication, with reduced precision to conserve power while still supporting a wide range of numerical values.

3. Grounds for Unpatentability

Ground 1: Obviousness over Dockser - Claims 1-2, 21-24, 26, and 28 are obvious over Dockser.

  • Prior Art Relied Upon: Dockser (Application # 2007/0203967).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Dockser disclosed all limitations of the challenged claims. Dockser taught a floating-point processor (FPP) that performs mathematical operations at a selectable, reduced precision to conserve power, particularly in battery-operated devices. This FPP was asserted to be the claimed LPHDR execution unit. Petitioner contended that Dockser’s FPP operates on standard IEEE-754 32-bit floating-point numbers, which inherently provide the high dynamic range required by claim 1. The low precision was achieved by dropping a selectable number of the least-significant bits from the mantissa of the operands, either by unpowering parts of the operand registers or parts of the multiplier logic. Petitioner asserted through software demonstration and algebraic analysis that Dockser’s example of retaining only 9 mantissa bits necessarily results in the minimum relative error (Y=0.05%) for the minimum fraction of inputs (X=5%) recited in claim 1.
    • Motivation to Combine (for §103 grounds): This ground relied on a single reference. Petitioner argued a person of ordinary skill in the art (POSITA) would have readily implemented Dockser's teachings using conventional, known components and methods, rendering the claims obvious.
    • Expectation of Success (for §103 grounds): A POSITA would have had a high expectation of success because Dockser's FPP used conventional floating-point principles and aimed to achieve the predictable result of power savings by reducing precision.

Ground 2: Obviousness over Dockser and Tong - Claims 1-2, 21-24, 26, 28, and 32-33 are obvious over Dockser in view of Tong.

  • Prior Art Relied Upon: Dockser (Application # 2007/0203967) and Tong (a June 2000 IEEE publication).
  • Core Argument for this Ground:
    • Prior Art Mapping: This combination relied on Dockser for the core LPHDR execution unit, as in Ground 1. Tong was introduced to provide specific, optimized levels of precision for certain applications. Tong taught that for many applications (e.g., speech recognition), precision could be significantly reduced to save power without meaningfully impacting accuracy, demonstrating that as few as 5 mantissa bits were sufficient. Tong also explicitly taught emulating different floating-point bitwidths in software to determine the optimal precision level for an application, which Petitioner argued rendered claim 33 (reciting software emulation) obvious.
    • Motivation to Combine (for §103 grounds): A POSITA would combine Dockser and Tong because both addressed the same problem: reducing power consumption in processors by lowering arithmetic precision. A POSITA would have been motivated to apply Tong's empirically determined optimal precision levels (e.g., 5 mantissa bits) to Dockser's selectable-precision FPP to achieve even greater, yet predictable, power savings in the mobile applications targeted by both references.
    • Expectation of Success (for §103 grounds): A POSITA would have reasonably expected success in applying Tong’s precision levels to Dockser’s architecture, as it involved adjusting a known design parameter (mantissa bitwidth) to achieve the expected outcome of reduced power consumption.

Ground 3: Obviousness over Dockser and MacMillan - Claims 1-26, 28, 36-61, and 63 are obvious over Dockser in view of MacMillan.

  • Prior Art Relied Upon: Dockser (Application # 2007/0203967) and MacMillan (Patent 5,689,677).

  • Core Argument for this Ground:

    • Prior Art Mapping: This combination again relied on Dockser for the core LPHDR execution unit. MacMillan was introduced to teach a parallel processing architecture (Single Instruction, Multiple Data or SIMD) that used multiple "floating point accelerators" operating in parallel to achieve "supercomputer performance." Petitioner argued that each of these accelerators was an execution unit. This combination was used to challenge claims requiring a plurality of LPHDR units (e.g., claims 3, 36).
    • Motivation to Combine (for §103 grounds): A POSITA would combine these references to create a system that is both fast and power-efficient. MacMillan taught using parallel processing to increase speed, while Dockser taught reducing precision to decrease power consumption. A POSITA would have been motivated to implement MacMillan’s parallel "floating point accelerators" using Dockser's power-saving FPPs to gain the benefits of both high performance and low power, a particularly desirable combination for the battery-operated personal devices mentioned in both references.
    • Expectation of Success (for §103 grounds): Success was predictable, as it involved substituting one known type of processing unit (a standard floating-point accelerator) with another known type (Dockser's power-saving FPP) within a parallel architecture to achieve the combined, predictable benefits of each.

  • Additional Grounds: Petitioner asserted an additional obviousness challenge (Ground 4) based on the combination of Dockser, Tong, and MacMillan, arguing it would have been obvious to implement the parallel processing system of MacMillan using Dockser's LPHDR units configured with the optimal precision levels taught by Tong.

4. Key Technical Contentions (Beyond Claim Construction)

  • "Statistical Mean" for Deterministic Circuits: Petitioner contended that for deterministic digital circuits, as disclosed in Dockser, the "statistical mean, over repeated execution" is simply the single, repeatable numerical output for any given input. The claim language was intended to also cover non-deterministic analog circuits but is met directly by the single output of a conventional deterministic digital circuit.
  • Error Thresholds as an Inherent Result: Petitioner argued that the claimed error thresholds (X≥5%, Y≥0.05%) were not a unique invention but an inherent and predictable consequence of reducing precision by dropping mantissa bits as taught by Dockser. This was supported by detailed software simulations and algebraic analyses showing that Dockser's example of retaining 9 mantissa bits would inherently meet and exceed the claimed error thresholds for a large percentage of valid inputs.

5. Arguments Regarding Discretionary Denial

  • Petitioner argued against discretionary denial under Fintiv, asserting that the factors weighed heavily in favor of institution. Key arguments included that the parallel district court litigation was in its infancy, with no trial date set and significant delays expected due to the global pandemic. Furthermore, party investment in the litigation was minimal, fact discovery was not advanced, and expert reports were not yet due. Petitioner also noted that the IPR challenges 61 claims not asserted in the litigation, reducing the overlap of issues and favoring a Board decision to promote patent system efficiency and prevent prejudice to the Petitioner.

6. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1-26, 28, 32-61, 63, and 67-70 of the 8,407,273 patent as unpatentable under 35 U.S.C. §103.