Microchip Technology Inc v. Bell Semiconductor LLC

1. Case Identification

• Case #: IPR2021-00191
• Patent #: 7,221,173
• Filed: November 16, 2020
• Petitioner(s): Microchip Technology Incorporated; Microsemi Corporation
• Patent Owner(s): Bell Semiconductor, LLC
• Challenged Claims: 1-10

2. Patent Overview

• Title: Method and Structures for Testing a Semiconductor Wafer Prior to Performing a Flip Chip Bumping Process
• Brief Description: The ’173 patent discloses an interface assembly for a semiconductor wafer designed to allow wafer-level testing prior to the flip-chip bumping process. The invention aims to prevent damage to bonding pads during probe testing by providing a conductive test pad that is integrally constructed with, but separate from, the bonding pad, eliminating the need for separate interconnect trace lines that could cause signal delays.

3. Grounds for Unpatentability

Ground 1: Claims 1-10 are anticipated by Mardi under 35 U.S.C. §102.

• Prior Art Relied Upon: Mardi (Patent 7,235,412).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Mardi discloses all limitations of claims 1-10. Mardi teaches an interface assembly for testing flip-chip semiconductor wafers before solder bumps are applied. It describes test pads (26A) and bond pads (22A) that are integrated as "separate regions" of a single "top conductor layer" (36). This structure corresponds to the ’173 patent’s claimed integral test and bonding pads without separate interconnect lines. Petitioner asserted that Mardi’s process flow (Fig. 6) explicitly shows testing the substrate (step 606) before the bumping process (step 614), satisfying the pre-bumping testing limitation. Dependent claims were allegedly met as Mardi describes various pad shapes, pad placement around a periphery, and multiple metal redistribution layers connected by vias.

Ground 2: Claims 1-4, 7, and 9 are anticipated by Lin under 35 U.S.C. §102.

• Prior Art Relied Upon: Lin (Patent 6,765,228).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner asserted that Lin discloses an integrated bonding pad with separate, non-overlapping areas for probing and bonding, anticipating the challenged claims. Lin’s single bonding pad (46) contains a "wire bonding area" (48) for bumping and a "probe needle contact area" (50) for testing. Because these are distinct regions of the same conductive structure, they are integral, coplanar, and constructed without interconnect testing lines, as claimed. Lin expressly teaches performing this parametric testing on a wafer prior to packaging and bump formation to "enhance wafer sort yield." For claim 7, Petitioner argued that Lin's "pad opening 44" through the passivation layer defines the region to be bumped (wire bonding area 48).

Ground 3: Claims 5-6 and 10 are obvious over Lin in view of Yong under 35 U.S.C. §103.

• Prior Art Relied Upon: Lin (Patent 6,765,228), Yong (Application # 2003/0173667).

• Core Argument for this Ground:

  • Prior Art Mapping: This ground addresses claims requiring multiple metal redistribution layers connected by vias. Petitioner argued Lin teaches the fundamental structure of an integral test and bond pad, while Yong supplies the well-known context for multi-layer interconnects. Yong discloses semiconductor devices with multiple metal layers (e.g., layers 28, 30, 32) connected through vias, teaching the structure of claim 6.
  • Motivation to Combine: A person of ordinary skill in the art (POSITA) would have been motivated to modify Lin's structure based on Yong's teachings. Yong teaches that an aluminum bond pad layer on top of a copper redistribution layer is not necessary, as the copper layer itself is strong enough for wire bonding. A POSITA would have been motivated to omit the separate aluminum layer in Lin's "prior art" embodiment to solder a bump directly to the underlying copper redistribution layer. This modification would simplify manufacturing and improve electrical performance by eliminating contact resistance between metal layers.
  • Expectation of Success: A POSITA would have had a reasonable expectation of success in combining the teachings. The modification represents a simple substitution of one known element (direct bonding to copper, taught by Yong) for another (bonding to an aluminum plating) to achieve the predictable results of improved electrical characteristics and manufacturing efficiency.

• Additional Grounds: Petitioner asserted additional obviousness challenges, including that claims 1-10 are obvious over Mardi in view of a POSITA’s general knowledge, and that claims 1-7 and 9-10 are obvious over Lin in view of a POSITA’s general knowledge. These grounds relied on arguments that implementing features like wafer-level testing and redistribution layers were common knowledge and predictable design choices for a POSITA.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under the Fintiv factors would be unwarranted. The petition was filed expeditiously, only five weeks after receiving preliminary infringement contentions in a related district court case.
• Petitioner contended the parallel district court case was in its infancy, with a trial date that was uncertain and likely to occur after a Final Written Decision (FWD) in the IPR.
• To prevent overlap, Petitioner stipulated that it would not pursue any ground in the district court that was raised or could have been reasonably raised in the IPR.
• Petitioner also argued that the complex semiconductor technology is better suited for resolution by the technically expert PTAB than by a jury of laypersons.

5. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 1-10 of the ’173 patent as unpatentable.