PTAB

IPR2021-00256

Samsung Electronics Co Ltd v. Trenchant Blade Technologies LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Multiple-Gate Device Structure and Method
  • Brief Description: The ’619 patent relates to multiple-gate metal-oxide semiconductor field-effect transistors (MOSFETs), specifically FinFET-type structures. The patent purports to describe forming a fully-depleted silicon-on-insulator (FD-SOI) device using less costly techniques, with the claims reciting a FinFET structure having a fin-like active region with rounded top corners.

3. Grounds for Unpatentability

Ground I: Anticipation of Claims 1, 3-7, 11, and 13-16 by Hieda

  • Prior Art Relied Upon: Hieda (Application # 2002/0011612).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Hieda’s twelfth embodiment discloses every limitation of the challenged claims. Hieda teaches a FinFET device comprising a semiconductor “fence” (the claimed active region) on a substrate, partially buried in and surrounded by an isolation material. A gate electrode wraps around the exposed portion of the fence via a “gate insulating film” (the claimed gate dielectric layer). Crucially, Hieda’s twelfth embodiment explicitly describes modifying the fence to have a “round of the top corner,” which directly teaches the key limitation added to the ’619 patent claims during prosecution to overcome prior art. Petitioner asserted that Hieda also expressly discloses the limitations of various dependent claims, including silicon oxynitride or high-k gate dielectrics (claims 3-6), specific dielectric thickness ranges (claim 7), polycrystalline silicon or metal gate electrodes (claims 11, 13), lightly doped source/drain extension regions (claim 14), and conductive silicide strapping over the source/drain regions (claims 15-16).

Ground II: Obviousness of Claims 1-11 and 13-16 over Hieda

  • Prior Art Relied Upon: Hieda (Application # 2002/0011612).
  • Core Argument for this Ground:
    • Prior Art Mapping: As an alternative to anticipation, Petitioner argued it would have been obvious to combine features from Hieda’s various disclosed embodiments (e.g., the first, twelfth, and fourteenth embodiments) to arrive at the claimed invention. The base FinFET structure is taught in the first embodiment, the rounded corners are taught in the twelfth, and the use of an SOI substrate is taught in the fourteenth.
    • Motivation to Combine: A POSITA would combine Hieda’s embodiments because the reference expressly states that its various embodiments “can be practiced alone or in an appropriate combination” and uses common reference numerals across different figures, suggesting interchangeability. A POSITA would be motivated to incorporate the rounded corners of the twelfth embodiment to gain its stated benefits of reducing electric field concentration and improving reliability. Similarly, a POSITA would be motivated to use an SOI substrate (fourteenth embodiment) for its well-known performance advantages.
    • Expectation of Success: A POSITA would have had a high expectation of success, as this combination involved routine design choices among a finite number of predictable solutions disclosed within a single, comprehensive reference to achieve known benefits.

Ground III: Obviousness of Claims 10 and 12 over Hieda in view of Murthy

  • Prior Art Relied Upon: Hieda (Application # 2002/0011612), Murthy (Patent 6,373,112).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground asserted that Hieda’s FinFET structure is rendered obvious by supplemental teachings from Murthy. For claim 10, which requires a gate dielectric thickness of less than 20 angstroms, Murthy expressly teaches a silicon oxide gate dielectric having a “thickness less than approximately 20 angstroms.” For claim 12, which requires a polycrystalline silicon germanium gate electrode, Murthy teaches replacing a conventional polycrystalline silicon gate with a polycrystalline silicon germanium gate to improve transistor performance by mitigating carrier depletion effects.
    • Motivation to Combine: A POSITA would combine Hieda with Murthy to improve the performance of Hieda’s disclosed device, consistent with the industry-wide goal of creating smaller and more efficient transistors. A POSITA would have looked to known techniques, such as those in Murthy, to thin the gate dielectric for better gate control (claim 10) and improve the gate electrode conductivity (claim 12).
    • Expectation of Success: The proposed modifications represented a simple substitution of one known component for an improved, but also well-known, alternative to achieve predictable performance enhancements.

  • Additional Grounds: Petitioner asserted additional obviousness challenges based on other combinations of Hieda's various embodiments and further combinations of Hieda and Murthy, relying on similar motivations.

4. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial would be improper under both 35 U.S.C. §325(d) and §314(a).
    • Under §325(d), Petitioner asserted that the primary prior art references, Hieda and Murthy, were not considered during the original prosecution, which focused on a reference that failed to teach the key limitation of rounded corners.
    • Under the Fintiv factors for §314(a), Petitioner argued for institution because the IPR petition was filed just 13 days after the parallel district court litigation commenced. This early filing means there has been minimal investment by the court and parties, and no trial date is scheduled. Furthermore, the district court case is a declaratory judgment action for non-infringement, creating no substantive overlap with the invalidity issues raised in the IPR.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-16 of Patent 6,720,619 as unpatentable.