Samsung Electronics Co Ltd v. Trenchant Blade Technologies LLC

1. Case Identification

• Case #: IPR2021-00258
• Patent #: 7,494,846
• Filed: December 4, 2020
• Petitioner(s): Samsung Electronics Co., Ltd.
• Patent Owner(s): Trenchant Blade Technologies, LLC.
• Challenged Claims: 1-16

2. Patent Overview

• Title: Method of Forming a Semiconductor Structure
• Brief Description: The ’846 patent describes a method for fabricating three-dimensional integrated circuits (3DICs) by stacking multiple identical semiconductor dies. To distinguish between the identical dies, each die includes a programmable identification (ID) circuit that is programmed with a unique address, purportedly reducing manufacturing complexity and cost compared to prior art methods.

3. Grounds for Unpatentability

Ground I: Anticipation of Claims 1, 3, 8, 9, and 11 under §102 over Matsuo

• Prior Art Relied Upon: Matsuo (Application # 2003/0062612).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Matsuo disclosed every limitation of the challenged claims. Matsuo taught a method for manufacturing a stacked semiconductor device by forming and stacking multiple identical memory chips (C1-C4). Each chip included a "holding circuit" (an identification circuit) that stores unique identification data to distinguish it from other chips in the stack. Petitioner contended Matsuo’s "through plugs" (PGs) penetrating each chip were functionally and structurally equivalent to the "through-silicon vias" (TSVs) recited in the claims for providing I/O conductive paths. Furthermore, Matsuo explicitly described programming the identification data into each chip's holding circuit (step S12) before the chips were physically stacked and assembled (step S17), directly teaching the sequence required by claim 3. Matsuo also disclosed steps of "thinning and dicing" (claim 8) and stacking additional identical dies (claim 9).

Ground II: Obviousness of Claims 4-7 under §103 over Matsuo in view of Farnworth

• Prior Art Relied Upon: Matsuo (Application # 2003/0062612) and Farnworth (Patent 6,841,883).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground focused on claims requiring the sawing of dies from different wafers. While Matsuo taught dicing chips from a wafer, Farnworth was introduced for its explicit teaching of using a "dicing saw" to singulate dice. Critically, Farnworth disclosed a wafer-bonding method where a "base wafer" and a "secondary wafer" are bonded together and then sawed, resulting in stacked dies originating from two different wafers. Petitioner argued that applying Farnworth’s well-known wafer sawing process to Matsuo’s stacking method rendered the claims obvious. For claim 5, Petitioner asserted it would have been obvious to adopt Farnworth’s “wafer-bond-then-saw” technique, which would result in the programming and bonding steps occurring before the final sawing step, as recited.
  • Motivation to Combine: A person of ordinary skill in the art (POSITA) would combine Matsuo and Farnworth as both addressed the same technical problem of manufacturing stacked semiconductor devices. Implementing Matsuo's dicing step with Farnworth's explicit dicing saw was a simple and predictable design choice, representing one of a few known methods for singulating dies.
  • Expectation of Success: A POSITA would have a reasonable expectation of success because the combination involved applying a standard, well-understood fabrication technique (sawing from multiple wafers) to a known device structure (Matsuo’s stacked dies) to achieve a predictable result.

Ground IV: Obviousness of Claims 2, 12-14, and 16 under §103 over Matsuo in view of Trezza

• Prior Art Relied Upon: Matsuo (Application # 2003/0062612) and Trezza (Application # 2006/0278992).

• Core Argument for this Ground:

  • Prior Art Mapping: This ground addressed limitations requiring vertically aligned I/O pads on opposite sides of the semiconductor dies. Petitioner argued that to the extent Matsuo’s disclosure of pads and bumps was insufficient, Trezza explicitly taught "through-chip connections" with "contact pads" on opposite sides of each die. Trezza’s pads were vertically aligned to bond with pads on adjacent dies, providing reliable electrical connections and acting as standoffs for proper clearance. Petitioner asserted that modifying Matsuo’s structure to incorporate Trezza’s superior pad-to-pad bonding technique would have been obvious. This combination also allegedly rendered claim 12 (a method of forming and operating) and its dependent claims obvious.
  • Motivation to Combine: A POSITA would combine the references to improve the reliability and performance of Matsuo's stacked die structure. Trezza’s direct pad bonding technique was presented as a known solution to improve electrical connections, reduce parasitic effects, and create stronger physical bonds compared to the bump-based connections in Matsuo. This addressed the fundamental goal of creating robust, high-density stacked devices.
  • Expectation of Success: The combination was a simple substitution of one known interconnection method (Trezza’s aligned pads) for another (Matsuo’s pads and bumps) to achieve the predictable benefits of improved electrical and mechanical performance.

• Additional Grounds: Petitioner asserted additional obviousness challenges, including combining Matsuo with Beffa (Patent 5,915,231) for blowing fuses to program ID circuits (Ground III), with Leedy (Application # 2005/0023656) for thinning only one die in a stack (Ground V), and with Suh (Application # 2007/0218678) as an alternative to Farnworth for wafer-bonding (Ground VI). A final ground combined Matsuo, Trezza, and Beffa (Ground VII).

4. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under §325(d) was inappropriate because the primary prior art references (Matsuo, Farnworth, Trezza) were not considered during the original prosecution. The examiner’s allowance was based on a finding that the prior art of record lacked specific bonding and vertical alignment limitations, which Petitioner contended the newly cited references expressly teach.
• Petitioner also argued against discretionary denial under Fintiv, noting the petition was filed just 14 days after the parallel district court litigation commenced. Petitioner asserted that the litigation was in its earliest stages with no trial date set, minimal investment by the parties, and no substantive overlap in issues, as the court case concerned non-infringement while the inter partes review (IPR) addresses validity.

5. Relief Requested

• Petitioner requested the institution of an IPR and the cancellation of claims 1-16 of the ’846 patent as unpatentable.