PTAB

IPR2021-00343

Micron Technology Inc v. Unification Technologies LLC

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Apparatus, System, and Method for Identifying Data That is No Longer in Use
  • Brief Description: The ’406 patent discloses methods for managing data in non-volatile storage, such as flash memory. The claimed invention involves receiving an indication that a data structure has been deleted by a user, where the indication uses a logical identifier mapped to a physical address, and then recording that the underlying data can be erased at a later time, thereby avoiding inefficient immediate-overwrite processes.

3. Grounds for Unpatentability

Ground 1: Claims 15-21 and 26-30 are obvious over Bennett in view of POSITA knowledge.

  • Prior Art Relied Upon: Bennett (Patent 7,624,239) and general knowledge of a Person of Ordinary Skill in the Art (POSITA).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Bennett disclosed all limitations of the challenged claims. Bennett taught a flash memory system that, upon receiving an erase command specifying logical sectors, would perform a "logical erase" for partial block erasures. This process involved setting a flag in a logical-to-physical Group Address Table (GAT) to designate the data as erased without immediately altering the physical data, allowing for actual erasure to occur later during a background process like garbage collection. Petitioner asserted this directly maps to the ’406 patent’s method of receiving an indication of deletion via a logical identifier and recording that the data can be erased.
    • Motivation to Combine: The combination is with the general knowledge of a POSITA. Petitioner contended that Bennett explicitly described logical erasing as "common" and a "standard, logical erase method." Therefore, a POSITA would have naturally understood and applied this common knowledge to implement the system described in Bennett, arriving at the claimed invention without inventive skill.
    • Expectation of Success: Success would have been expected because logical erasing was a well-understood and standard technique for managing flash memory, which was known to have lengthy physical erase times.

Ground 2: Claims 15-21 and 26-30 are obvious over Suda in view of POSITA knowledge.

  • Prior Art Relied Upon: Suda (Patent 7,057,942) and general knowledge of a POSITA.
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued Suda taught a memory device that manages data erasure by using "erasure area pointers" upon receiving an erase command that designates a logical address. These pointers place the corresponding data range into a "virtual erased" state. While the physical data remains temporarily, any attempt to read it returns an "initial-value" (empty data). Suda also disclosed a logical-to-physical address table. Petitioner asserted this system of receiving an erase command with a logical identifier and using pointers to mark data for future erasure meets the key limitations of the challenged claims.
    • Motivation to Combine: The combination relies on a POSITA's general knowledge. A POSITA would have recognized Suda's "virtual erased" state as another implementation of the common logical erase concept. The motivation was to avoid lengthy physical erase cycles, a well-known problem that Suda explicitly addressed, using techniques that were part of the general skill in the art.
    • Expectation of Success: A POSITA would have had a high expectation of success, as Suda provided a concrete, functional system for implementing a logical erase process to improve memory device performance.

Ground 3: Claims 21, 26, and 28 are obvious over Suda in view of SwSTE'05 and POSITA knowledge.

  • Prior Art Relied Upon: Suda (Patent 7,057,942), SwSTE'05 (an IEEE conference paper on flash memory mapping structures), and general knowledge of a POSITA.
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground builds upon Suda to address specific dependent claims. SwSTE'05, a survey of flash memory technologies, explicitly taught using a "valid bit" associated with each block to indicate whether the data is valid or invalid. Petitioner argued that to meet the limitation of claim 21 ("mark a data packet... invalid"), a POSITA would find it obvious to incorporate the standard valid bit from SwSTE'05 into Suda's system. For claims 26 and 28, which require a "storage recovery module" (interpreted as performing garbage collection), Petitioner argued that Suda's "erasure processing" is a form of garbage collection. Furthermore, SwSTE'05 provided an explicit, standard definition and process for garbage collection that a POSITA could have readily applied to Suda's system.
    • Motivation to Combine: A POSITA would combine the teachings because both Suda and SwSTE'05 addressed the same field of flash memory management and performance optimization. A POSITA would have been motivated to implement the specific, well-documented techniques from the SwSTE'05 survey (like valid bits and standardized garbage collection) into Suda's system to improve its functionality using predictable, industry-standard methods.
    • Expectation of Success: Success was predictable because the proposed modifications involved combining Suda's system with standard, fundamental building blocks of flash memory management that were known to be compatible and effective.

4. Key Claim Construction Positions

  • Petitioner dedicated a section to claim construction disputes from parallel litigation, noting they do not affect the outcome of the Petition.
  • For terms Petitioner considered indefinite (e.g., "marking module," "index module"), they adopted the Patent Owner's proposed constructions for the purpose of their obviousness analysis.
  • For "logical identifier," Petitioner proposed "an identifier maintained by a computer attached to the storage medium used to identify the logical location of data," whereas the Patent Owner proposed "information that identifies a particular set of data that is not the physical address of the data." Petitioner argued its invalidity contentions held under either construction.

5. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under Fintiv was not warranted due to the circumstances of the parallel district court litigation.
  • The core argument rested on a stipulation that, if the IPR is instituted, Petitioners will not pursue in district court any invalidity ground that was raised or could have been reasonably raised in the IPR.
  • Petitioner also asserted that the parallel litigation was in a very early stage, with no substantive rulings, limited discovery, and an uncertain trial date, thus weighing heavily in favor of institution.

6. Relief Requested

  • Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 15-21 and 26-30 of the ’406 patent as unpatentable.