Intel Corp v. Flash Control LLC

1. Case Identification

• Case #: IPR2021-00348
• Patent #: 9,257,184
• Filed: January 13, 2021
• Petitioner(s): Intel Corporation
• Patent Owner(s): Flash-Control, LLC
• Challenged Claims: 1-16

2. Patent Overview

• Title: Nonvolatile Memory System
• Brief Description: The ’184 patent discloses a nonvolatile memory system that uses a coupled volatile memory (buffer) and one or more controllers to manage data operations. The core technique involves a read-modify-write process where, upon modification, data is written to a new physical location in the nonvolatile memory while its associated logical (addressable) location remains unchanged.

3. Grounds for Unpatentability

Ground 1: Claims 1-3, 8, 9, and 11-16 are obvious over Park, ONFI, and Aasheim.

• Prior Art Relied Upon: Park (Application # 2006/0227607), ONFI (Open NAND Flash Interface Specification, Rev. 1.0, Dec. 2006), and Aasheim (Application # 2003/0163630).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that the combination of these three references taught every element of the challenged claims. Park disclosed the core architecture of a nonvolatile memory system, including a nonvolatile flash memory, a volatile buffer memory (SRAM or DRAM), and a controller for managing data exchanges, including copyback operations. ONFI, a flash memory interface standard, provided the detailed command set for implementing operations Park only mentioned generally, specifically teaching a "Copyback with data modification" function. Aasheim taught a flash driver with logical-to-physical address mapping, which allows data to be moved to new physical locations for wear-leveling and efficiency while maintaining a constant logical address for the host system.
  • Motivation to Combine: A POSITA would combine Park and ONFI because Park described copyback operations conceptually but lacked implementation details; a POSITA would naturally look to an industry standard like ONFI to provide the specific command set. A POSITA would further combine Aasheim's logical-to-physical mapping to improve the Park/ONFI system's performance, data integrity, and longevity through wear-leveling. Aasheim's mapping provided the exact mechanism to fulfill the claimed function of writing modified data to a new physical location while preserving the logical address.
  • Expectation of Success: A POSITA would have a high expectation of success because all three references operate in the same field of NAND flash memory. Park’s architecture was designed to support copyback, ONFI provided a standardized interface for such operations, and Aasheim's mapping was "agnostic" and designed to work with most flash devices. The combination represented the integration of well-known, compatible techniques to achieve predictable improvements.

Ground 2: Claim 4 is obvious over Park, ONFI, and Aasheim in view of Li.

• Prior Art Relied Upon: Park, ONFI, Aasheim, and Li (Application # 2006/0077706).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground built upon the Park/ONFI/Aasheim combination from Ground 1. Claim 4 requires the nonvolatile memory to be a "phase change memory." Li explicitly disclosed phase change memory as a known type of nonvolatile memory with benefits such as high speed and long endurance.
  • Motivation to Combine: Petitioner argued this was a simple substitution of one known element for another. Park itself disclosed several types of nonvolatile memory beyond NAND flash. A POSITA would have been motivated to substitute the flash memory in the base combination with Li's phase change memory to gain its known advantages. This was a predictable design choice from a finite number of known nonvolatile memory technologies.

Ground 3: Claims 5-7 are obvious over Park, ONFI, and Aasheim in view of Kilbuck.

• Prior Art Relied Upon: Park, ONFI, Aasheim, and Kilbuck (Application # 2005/0204091).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground also built on the base combination from Ground 1. Claims 5, 6, and 7 respectively require the nonvolatile memory to be a "magnetic memory," "ferroelectric memory," or "molecular memory." Kilbuck disclosed a nonvolatile memory system and expressly taught that memory types such as MRAM (magnetic), FeRAM (ferroelectric), and Molecular Memory were known alternatives that could be substituted for NAND flash memory.
  • Motivation to Combine: The motivation was again a simple and obvious substitution. Kilbuck explicitly taught that using these alternative memory technologies in place of flash memory would have been "apparent to those skilled in the art." A POSITA would have been motivated to make such a substitution to leverage the different characteristics of these memory types within the established Park/ONFI/Aasheim architecture.

Additional Grounds: Petitioner asserted an additional obviousness challenge for claim 10 based on the Park/ONFI/Aasheim combination in view of Lee (Patent 6,801,468). Lee taught using pseudo static RAM (pSRAM) as a type of volatile memory. Petitioner argued a POSITA would be motivated to substitute the SRAM/DRAM in Park with Lee's pSRAM to gain its described benefits, such as improved speed and capacity.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under §314(a) and §325(d) would be inappropriate. It asserted that the petition presented unique grounds not raised in a parallel IPR filed by another party (IPR2020-01709). Furthermore, the co-pending district court litigation involving the ’184 patent had been stayed indefinitely, meaning an IPR would be a more efficient and effective alternative to resolve the validity dispute without appreciable duplication of effort.

5. Relief Requested

• Petitioner requested institution of an IPR and cancellation of claims 1-16 of the ’184 patent as unpatentable.