PTAB

IPR2021-00349

Intel Corp v. Flash Control LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Nonvolatile memory system
  • Brief Description: The ’219 patent describes a nonvolatile memory system that uses a volatile random access memory as a buffer. The system performs read and write operations, including moving data from one physical location to another within the nonvolatile memory while an associated logical address remains unchanged through address mapping.

3. Grounds for Unpatentability

Ground 1: Claims 1, 2, 7, 8, and 10-13 are obvious over Park, ONFI, and Aasheim

  • Prior Art Relied Upon: Park (Application # 2006/0227607), ONFI (Open NAND Flash Interface Specification, Rev. 1.0, Dec. 2006), and Aasheim (Application # 2003/0163630).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued this combination teaches every element of the challenged claims. Park taught the core architecture of a nonvolatile memory system, including a nonvolatile flash memory, a volatile buffer memory (e.g., SRAM or DRAM), and a controller managing data flow between them. ONFI, a standardized interface specification, taught the specific command set for performing a "copyback with data modification" operation, where data is read from nonvolatile memory into a buffer (a page register), modified in the buffer, and written back to a new location in the nonvolatile memory. Aasheim taught a flash driver implementing logical-to-physical address mapping, which allows data to be written to a new physical location while maintaining the same logical address, a key feature of the ’219 patent’s claims.
    • Motivation to Combine: A POSITA would combine Park with ONFI because Park described data exchange operations at a high level, and the ONFI standard provided the detailed, standardized command set needed to implement such operations predictably in Park's architecture. A POSITA would further add Aasheim’s logical-to-physical mapping to the Park/ONFI system to gain well-known benefits such as improved efficiency, wear-leveling, and data integrity by providing flexibility in where data is physically stored during copyback or write operations. The combination was a predictable integration of known solutions to improve a conventional memory system.
    • Expectation of Success: A POSITA would have a reasonable expectation of success because all three references relate to standard NAND flash memory systems. ONFI is a standardized interface designed for a range of flash devices like Park’s, and Aasheim taught its address mapping technique was "agnostic" and could support "most, if not all, flash devices."

Ground 2: Claim 3 is obvious over Park, ONFI, and Aasheim in view of Li

  • Prior Art Relied Upon: Park (Application # 2006/0227607), ONFI, Aasheim (Application # 2003/0163630), and Li (Application # 2006/0077706).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground asserted that the base combination of Park/ONFI/Aasheim rendered claim 1 obvious, and that Li further supplied the limitation of claim 3: a "phase change memory." Li explicitly disclosed phase change memory as a type of non-volatile memory with benefits like high read/write speed and endurance.
    • Motivation to Combine: A POSITA would be motivated to substitute the flash memory in the Park/ONFI/Aasheim combination with the phase change memory taught by Li. Petitioner argued this was a simple substitution of one known non-volatile memory type for another to gain the known benefits described in Li. Park itself listed several types of non-volatile memory, suggesting interchangeability to a POSITA.

Ground 3: Claims 4-6 are obvious over Park, ONFI, and Aasheim in view of Kilbuck

  • Prior Art Relied Upon: Park (Application # 2006/0227607), ONFI, Aasheim (Application # 2003/0163630), and Kilbuck (Application # 2005/0204091).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground addressed claims 4-6, which specified magnetic, ferroelectric, and molecular memory, respectively. Petitioner argued Kilbuck disclosed these specific types of non-volatile memory (MRAM, FeRAM, and Molecular Memory) and taught that they were known alternatives to NAND flash memory.
    • Motivation to Combine: The motivation was again based on simple substitution. Kilbuck expressly taught that using these alternative memory technologies in a system with a buffer and controller (like Park's) would be "apparent to those skilled in the art." A POSITA would have found it obvious to substitute these known memory types into the base combination to obtain a predictable result.

Ground 4: Claim 9 is obvious over Park, ONFI, and Aasheim in view of Lee

  • Prior Art Relied Upon: Park (Application # 2006/0227607), ONFI, Aasheim (Application # 2003/0163630), and Lee (Patent 6,801,468).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground targeted claim 9, which required the volatile memory to be a "pseudo static RAM" (PSRAM). Lee disclosed using PSRAM, explaining its benefits include improved data read/write speeds and larger capacity than standard SRAM.
    • Motivation to Combine: A POSITA would be motivated to use Lee's PSRAM as the volatile buffer memory in the Park/ONFI/Aasheim combination to achieve the known benefits of increased speed and capacity. Since Park already disclosed using SRAM or DRAM for its buffer, substituting another known RAM variant like PSRAM was an obvious design choice.

4. Arguments Regarding Discretionary Denial

  • Petitioner argued against discretionary denial under Fintiv. It contended that the parallel district court case was stayed indefinitely pending appeal of a related case, meaning no trial date was set and there would be no duplication of effort. Petitioner also asserted that its grounds were unique and not duplicative of those in a separate IPR filed by another party (Micron) against the same patent.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-13 of the ’219 patent as unpatentable under 35 U.S.C. §103.