PTAB

IPR2021-00591

Samsung Electronics Display Co Ltd v. Solas OLED Ltd

Key Events

Petition

petition

Title: OLED Display Driving Circuitry
Brief Description: The ’880 patent discloses an active matrix organic light-emitting diode (OLED) display. The technology involves circuitry that controls pixel operation by switching a drive voltage between high and low levels to define distinct "display" (on) and "non-display" (off) periods for rows of pixels. During the non-display period, a bias elimination state clears previously stored brightness data before new data is written for the next display period.

Prior Art Relied Upon: Miyazawa (Application # 2005/0083270).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Miyazawa discloses all elements of the challenged claims. Miyazawa describes an active matrix OLED display with a pixel circuit architecture that includes a power line control circuit for switching pixels between display-on and display-off states. Its timing diagram explicitly shows a "bias-elimination/reverse-bias period" occurring during the display-off state. This period is used to eliminate a previously set bias state corresponding to display data before a writing/selection period programs the next gradation signal, directly mapping to the core limitations of independent claims 1, 3, and 25.
- Motivation to Combine (for §103 grounds): For the alternative obviousness ground (1a), Petitioner asserted that to the extent any minor limitation was not explicitly disclosed, a person of ordinary skill in the art (POSA) would have been motivated to modify Miyazawa using well-known OLED design techniques to achieve more accurate luminance programming and emission.
- Expectation of Success (for §103 grounds): A POSA would have had a reasonable expectation of success as any modifications would entail simple, predictable design choices.

Prior Art Relied Upon: Morosawa (WO 2004/040543).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner contended that Morosawa, like the ’880 patent, discloses an OLED display panel with voltage, data, and scanning drivers that turn pixels on and off. Morosawa explicitly teaches that its pixel driver circuit (Fig. 16) can be improved by incorporating a reset circuit (Fig. 38) to enhance operation. Petitioner argued this taught combination provides a bias-elimination mechanism, as the reset circuit drains charge from the pixel's capacitor before each write operation. This functionality, disclosed entirely within Morosawa, anticipates the key limitations of the independent claims related to setting pixels to a non-display state that includes eliminating a prior bias state.
- Motivation to Combine (for §103 grounds): For the obviousness ground (2a), the motivation to combine Morosawa’s own circuit disclosures was self-evident, as Morosawa explicitly taught that the circuits could be used together to improve performance.
- Expectation of Success (for §103 grounds): Success was expected because Morosawa expressly described how the different circuit arrangements could be applied and combined.

Prior Art Relied Upon: Morosawa (WO 2004/040543), Shirasaki (WO 2004/086347).
Core Argument for this Ground:
- Prior Art Mapping: This ground built upon the teachings of Morosawa by adding Shirasaki's disclosure of grouping multiple rows of pixels. Shirasaki teaches driving a group of adjacent rows with a common power supply line and selecting them with a common scanning line to improve display quality. This directly addresses the limitations in claims 18 and 34, which require the display pixels to be "divided into a plurality of groups each including a plurality of rows" that are operated on simultaneously.
- Motivation to Combine: Petitioner argued a POSA would combine these references to gain known benefits. Shirasaki explicitly teaches that grouping rows allows for a longer write time, which improves image quality and enables higher resolution displays. A POSA would have been motivated to apply this established technique to the display architecture of Morosawa to achieve these same advantages.
- Expectation of Success: The combination was argued to be a simple and predictable modification of Morosawa’s circuit, involving tying multiple rows to common power and scan lines as taught by Shirasaki.
Additional Grounds: Petitioner asserted additional obviousness challenges, including combining Morosawa, Shirasaki, and Koyama (Application # 2003/0197664) for claims 24 and 40, and combining Morosawa and Hector (Patent 7,564,433) for claims 15-17.

Petitioner argued that discretionary denial under Fintiv was not warranted. It asserted that the co-pending district court case was stayed pending a parallel ITC investigation. Petitioner contended that ITC proceedings carry less weight in the Fintiv analysis because the ITC cannot invalidate claims and uses a different burden of proof. Furthermore, the ITC action was in its early stages, limiting the investment by the parties and the court. Petitioner also argued that the strong merits of the invalidity grounds presented in the petition weighed heavily in favor of institution.

Petitioner requested the institution of an inter partes review and the cancellation of claims 1-40 of the ’880 patent as unpatentable.