Taiwan Semiconductor Mfg Co Ltd v. Arbor Global Strategies LLC

1. Case Identification

• Case #: IPR2021-00736
• Patent #: 7,282,951
• Filed: April 5, 2021
• Petitioner(s): Taiwan Semiconductor Manufacturing Company Limited
• Patent Owner(s): Arbor Global Strategies LLC
• Challenged Claims: 1-2, 4-6, 8-29

2. Patent Overview

• Title: Reconfigurable Processor Module Comprising Hybrid Stacked Integrated Circuit Die Elements
• Brief Description: The ’951 patent discloses a reconfigurable processor module created by stacking different types of thinned integrated circuit die elements, such as a microprocessor, memory, and a field programmable gate array (FPGA). These stacked elements are interconnected using contacts that traverse the thickness of each die.

3. Grounds for Unpatentability

Ground 1: Obviousness over Zavracky, Chiricescu, and Akasaka - Claims 1-2, 4-6, 8-24, 27, and 29 are obvious over Zavracky in view of Chiricescu and Akasaka.

• Prior Art Relied Upon: Zavracky (Patent 5,656,548), Chiricescu (a 1998 IEEE article), and Akasaka (a 1986 IEEE article).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that the combination of these references taught all limitations of the challenged claims. Zavracky disclosed the core concept of vertically stacking different types of integrated circuit functional elements, including programmable logic devices, memory, and microprocessors, and interconnecting them with through-layer vias. Chiricescu, which explicitly builds on Zavracky's technology, taught using a stacked memory layer to accelerate the reconfiguration of a stacked FPGA, meeting limitations related to accelerating memory references. Akasaka taught 3D integrated circuits with "tens of thousands of via holes" distributed across the surface of the die, rather than just at the periphery, to improve signal processing speed, thereby satisfying the limitation of "contact points distributed throughout the surfaces."
  • Motivation to Combine: A POSITA would combine Zavracky and Chiricescu because Chiricescu expressly referenced Zavracky's work to solve the known problem of high FPGA configuration time, making the combination a logical design choice. A POSITA would be further motivated to incorporate Akasaka's teachings to gain the predictable benefits of massively parallel, distributed interconnections—namely, increased bandwidth and processing speed—for the stacked module taught by Zavracky and Chiricescu.
  • Expectation of Success: Petitioner asserted a POSITA would have had a reasonable expectation of success because Chiricescu was a direct extension of Zavracky's work from the same research group, and Akasaka taught a well-understood method for increasing interconnect density with predictable performance improvements.

Ground 2: Obviousness over Zavracky, Chiricescu, Akasaka, and Trimberger - Claim 25 is obvious over the combination of Ground 1 in view of Trimberger.

• Prior Art Relied Upon: Zavracky (Patent 5,656,548), Chiricescu (a 1998 IEEE article), Akasaka (a 1986 IEEE article), and Trimberger (a 1997 IEEE article).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground adds Trimberger to the primary combination to address claim 25, which requires the memory array to be "functional as block memory for said processing element." Trimberger explicitly taught using on-chip memory that is "accessible as block RAM for applications" running on an FPGA, allowing the memory to be efficiently used as a large block of RAM by the FPGA logic.
  • Motivation to Combine: A POSITA, seeking to support FPGA applications in the Zavracky-Chiricescu-Akasaka stack that require fast local memory, would have been motivated to implement the block memory taught by Trimberger. Using a separate, dedicated memory element as block memory was a known, silicon-efficient technique to enhance FPGA functionality, and stacking it nearby as taught by the primary combination would ensure high-speed access.
  • Expectation of Success: Applying Trimberger's known use of memory as block memory to the primary combination would have been a straightforward application of established engineering principles to improve the memory options of the stacked FPGA system.

Ground 3: Obviousness over Zavracky, Chiricescu, Akasaka, and Satoh - Claim 26 is obvious over the combination of Ground 1 in view of Satoh.

• Prior Art Relied Upon: Zavracky (Patent 5,656,548), Chiricescu (a 1998 IEEE article), Akasaka (a 1986 IEEE article), and Satoh (WO 00/62339).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground adds Satoh to the primary combination to address claim 26, which requires the contact points to be "further functional to provide test stimulus" from the FPGA to another element. Satoh taught using an FPGA's variable logic circuit to generate a specified test signal and supply it to an on-chip memory circuit to test for faults.
  • Motivation to Combine: A POSITA would have recognized that testing complex 3D stacked modules is crucial for improving manufacturing yield and avoiding the expense of "dead" chips. Satoh provided a known and praised method for using the existing, reconfigurable FPGA to test co-stacked memory, which would have been a predictable and cost-effective solution to apply to the primary combination, avoiding the expense, real estate, and complexity of a separate testing chip.
  • Expectation of Success: A POSITA would have had a reasonable expectation of success as using an FPGA for testing was a well-known technique, and its application was not dependent on whether the chip was 2D or 3D. The result would be a predictable application of a known testing method to the 3D stack.
• Additional Grounds: Petitioner asserted an additional obviousness challenge against claim 28 based on the primary combination in view of Alexander (a 1995 IEEE article), which taught stacking multiple FPGA dies for parallel processing applications.

4. Arguments Regarding Discretionary Denial

• Petitioner argued against discretionary denial under §325(d), stating the prior art combinations were not considered by the examiner during prosecution and are not cumulative to the cited art.
• Petitioner also argued against discretionary denial under Fintiv, asserting that the co-pending district court litigation trial date (May 23, 2022) was set for months after the Board’s projected Final Written Decision (March 2022). This timeline, along with minimal investment by the court in patentability issues to date, weighed strongly in favor of institution to promote efficiency and fairness.

5. Relief Requested

• Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 1-2, 4-6, and 8-29 of the ’951 patent as unpatentable.