Taiwan Semiconductor Mfg Co Ltd v. Arbor Global Strategies LLC

1. Case Identification

• Case #: IPR2021-00737
• Patent #: RE42,035
• Filed: April 5, 2021
• Petitioner(s): Taiwan Semiconductor Manufacturing Company Limited
• Patent Owner(s): Arbor Global Strategies LLC
• Challenged Claims: 1-38

2. Patent Overview

• Title: Reconfigurable Processor Module Comprising Hybrid Stacked Integrated Circuit Die Elements
• Brief Description: The ’035 patent describes a reconfigurable processor module created by stacking thinned integrated circuit die elements, such as a microprocessor, memory, and a field-programmable gate array (FPGA). These stacked dies are interconnected using contacts that traverse the thickness of the individual die elements.

3. Grounds for Unpatentability

Ground 1: Obviousness over Zavracky, Chiricescu, and Akasaka

• Legal Basis: Claims 1-30, 33, 36, and 38 are obvious over Zavracky in view of Chiricescu and Akasaka.
• Prior Art Relied Upon: Zavracky (Patent 5,656,548), Chiricescu (a 1998 IEEE article), and Akasaka (a 1986 IEEE article).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that the combination teaches all elements of the challenged claims. Zavracky taught vertically stacking and interconnecting different integrated circuit die elements, including programmable logic devices (PLDs), microprocessors, and memory, to form a three-dimensional processor. Chiricescu, which explicitly references Zavracky’s technology, taught a 3-D chip stacking an FPGA with a memory layer to significantly improve FPGA reconfiguration time. To meet the limitation of distributed contacts traversing the die thickness, Petitioner asserted Akasaka, which taught 3-D ICs using "tens of thousands of via holes" distributed across the die surface to increase connectivity, improve signal processing speed, and enable parallel processing.
  • Motivation to Combine: A POSITA would combine Zavracky and Chiricescu because Chiricescu explicitly builds on Zavracky's work to solve the known problem of high FPGA configuration time, a predictable improvement. A POSITA would further incorporate Akasaka’s high-density, distributed via holes into the Zavracky/Chiricescu stack to achieve the predictable benefits of increased bandwidth and processing speed for parallel processing applications, an advantage Akasaka itself promoted.
  • Expectation of Success: A POSITA would have a reasonable expectation of success, as the combination involved applying known techniques (high-density interconnects, stacked memory for reconfiguration) to a known 3-D processor architecture to achieve the predictable results of improved performance and faster reconfiguration.

Ground 2: Obviousness over Core Combination in view of Trimberger

• Legal Basis: Claims 31, 32, and 34 are obvious over Zavracky, Chiricescu, and Akasaka in view of Trimberger.
• Prior Art Relied Upon: The references from Ground 1, plus Trimberger (a 1997 IEEE article).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground added Trimberger to address claim limitations requiring a memory array that is functional as "block memory." Trimberger taught a time-multiplexed FPGA where on-chip memory is accessible as "block RAM" for applications running on the FPGA, allowing efficient use of memory resources.
  • Motivation to Combine: Petitioner argued that a POSITA seeking to support FPGA applications requiring fast local memory within the 3-D stack from the primary combination would have been motivated to incorporate Trimberger's teaching. Using dedicated block memory was a known, silicon-efficient method for improving FPGA performance for certain tasks.

Ground 3: Obviousness over Core Combination in view of Satoh

• Legal Basis: Claim 35 is obvious over Zavracky, Chiricescu, and Akasaka in view of Satoh.
• Prior Art Relied Upon: The references from Ground 1, plus Satoh (WO 00/62339).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground added Satoh to address claim 35’s limitation that the contact points are functional to provide a "test stimulus" from the FPGA to another die element. Satoh taught configuring an FPGA to generate test signals for testing co-located memory circuits, thereby improving yield and productivity.
  • Motivation to Combine: A POSITA would recognize that stacking multiple dies increases the risk of module failure and the need for testing. Satoh provided a known method for using the FPGA already present in the primary combination to test the stacked memory, which was a predictable and cost-effective solution that avoided the expense and complexity of a separate testing chip.

Ground 4: Obviousness over Core Combination in view of Alexander

• Legal Basis: Claim 37 is obvious over Zavracky, Chiricescu, and Akasaka in view of Alexander.
• Prior Art Relied Upon: The references from Ground 1, plus Alexander (a 1995 conference proceeding).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground added Alexander to address claim 37’s limitation requiring a third integrated circuit die element that includes another field programmable gate array. Alexander taught building a 3-D FPGA by stacking multiple 2-D FPGA dies.
  • Motivation to Combine: For parallel processing applications, a POSITA would have sought to enhance the computational power of the primary combination. Alexander taught that stacking multiple FPGAs was a preferable alternative to slower software-based solutions or inflexible custom hardware. A POSITA would therefore be motivated to add another FPGA layer as taught by Alexander to the 3-D stack.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial would be inappropriate under both 35 U.S.C. §325(d) and §314(a). The prior art combinations asserted in the petition were never considered by the USPTO during prosecution. Furthermore, Petitioner argued that the Fintiv factors weighed in favor of institution because the trial date in a parallel district court proceeding was scheduled for well after the statutory deadline for a Final Written Decision (FWD) in the IPR. Petitioner also submitted a stipulation to not pursue the same invalidity grounds in the district court if the IPR is instituted, mitigating concerns of parallel proceedings.

5. Relief Requested

• Petitioner requested institution of an inter partes review (IPR) and cancellation of claims 1-38 of the ’035 patent as unpatentable.