PTAB

IPR2021-00752

Microchip Technology Inc v. HD Silicon Solutions LLC

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Petition

1. Case Identification

2. Patent Overview

  • Title: Metal Stack for Local Interconnect Layer
  • Brief Description: The ’033 patent describes a method for forming a local interconnect layer in a semiconductor integrated circuit. The disclosed method involves depositing a first film of titanium nitride (TiN) over an oxide layer, followed by depositing a second film of tungsten (W) over the TiN film to form a conductive metal stack.

3. Grounds for Unpatentability

Ground 1: Obviousness over Trivedi in view of Joo - Claims 2-6, 15, and 16 are obvious over Trivedi in view of Joo.

  • Prior Art Relied Upon: Trivedi (Patent 5,847,463) and Joo (Patent 6,534,401).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Trivedi taught the foundational method of forming a local interconnect with a TiN barrier layer deposited over various oxide layers, followed by a tungsten-silicide layer. While Trivedi disclosed sputtering for the TiN layer and chemical vapor deposition (CVD) for the tungsten-silicide layer, Petitioner asserted Joo supplied the teachings for claims requiring in-situ sputtering. Joo taught that a TiN barrier layer and an overlying tungsten film can both be deposited by PVD (a sputtering process) or CVD. This made depositing both films in the same tool or chamber (in-situ), as required by claims 2 and 15, an obvious choice for manufacturing efficiency. Furthermore, Joo disclosed specific thickness ranges for its TiN layer (e.g., <100Å) and tungsten layer (e.g., 200-700Å) that Petitioner argued would render the thickness limitations of claims 4-6 and 16 obvious.
    • Motivation to Combine: A POSITA would combine Trivedi and Joo because both references address the same technical problem of fabricating semiconductor interconnects using a TiN barrier layer under a tungsten-based conductive layer. A POSITA would be motivated to apply Joo’s specific teachings on deposition methods (PVD for both layers) and layer thicknesses to Trivedi's process to improve manufacturing efficiency, reduce complexity and cost, and achieve predictable, functional, low-resistance interconnects.
    • Expectation of Success: Petitioner argued a POSITA would have a high expectation of success, as the combination involved applying known deposition techniques (PVD) and configuring layer thicknesses as taught by Joo to a similar, known structure from Trivedi to achieve the predictable benefits of improved manufacturability.

Ground 2: Obviousness over Trivedi in view of Yang - Claim 8 is obvious over Trivedi in view of Yang.

  • Prior Art Relied Upon: Trivedi (Patent 5,847,463) and Yang (a 1997 IEDM Technical Digest publication).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner contended that while Trivedi’s taught metal stack inherently possesses some sheet resistance, it did not specify a value. Yang was argued to remedy this deficiency by explicitly teaching TiN/W stacks and providing measured performance data. Specifically, Yang reported a sheet resistance of 2.06 Ω/sq for a PVD TiN and CVD W stack, a value well below the claimed threshold of "equal to or less than about 10 Ohm/sq" in claim 8.
    • Motivation to Combine: A POSITA would be motivated to look to a reference like Yang to optimize the electrical properties of the interconnect structure taught by Trivedi. Given that low sheet resistance is a critical property for an interconnect, a POSITA would combine Trivedi’s structure with Yang's teachings on materials and thicknesses to predictably achieve the low sheet resistance values demonstrated in Yang.
    • Expectation of Success: Petitioner asserted success would be predictable because sheet resistance is a fundamental physical property of a given material stack. Yang provided concrete experimental data for a nearly identical TiN/W stack, giving a POSITA confidence that applying its parameters to Trivedi's structure would yield a similarly low sheet resistance.

Ground 3: Obviousness over Trivedi in view of Lien - Claims 2, 11, and 12 are obvious over Trivedi in view of Lien.

  • Prior Art Relied Upon: Trivedi (Patent 5,847,463) and Lien (Patent 6,103,623).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground focused on the method's etching steps and in-situ deposition. Petitioner argued Trivedi disclosed the basic stack and a two-step etch process (etching the second film using the first as an etch stop, then etching the first film using the underlying oxide as an etch stop). Lien was argued to provide the specific, well-known chemistries for such a process. Lien taught etching a tungsten layer (the second film) with a fluorine-based etchant like SF6 (claim 11) and etching a TiN layer (the first film) using a chlorine-based etchant (claim 12). Lien also explicitly taught forming its TiN and tungsten layers via in-situ CVD deposition (claim 2).
    • Motivation to Combine: A POSITA would combine Trivedi and Lien to implement an effective and well-understood method for patterning the metal interconnect stack. Using Lien’s specific fluorine- and chlorine-based etchants for tungsten and TiN, respectively, was presented as a standard, predictable, and logical choice for performing the etching steps generally described in Trivedi.
    • Expectation of Success: Success would be highly expected, as the combination merely involved applying known, conventional etchants to their corresponding, well-known materials within a standard semiconductor fabrication sequence.
  • Additional Grounds: Petitioner asserted further obviousness challenges for claim 7 over Trivedi, Joo, and Yang; for claim 13 over Trivedi and Johnson; and for claim 17 over Trivedi, Joo, and Johnson, relying on similar motivations to improve performance and manufacturability by incorporating known material properties and process monitoring techniques.

4. Arguments Regarding Discretionary Denial

  • Petitioner argued against discretionary denial under Fintiv, asserting that multiple factors weighed in favor of institution. The petition was filed early in a parallel district court proceeding, before a trial date was set and before any significant investment of resources by the court or the parties. Petitioner contended that the Board would likely reach a Final Written Decision before a potential trial, promoting judicial efficiency. The petition’s challenge to all 17 claims of the patent was also cited as a factor favoring institution, as it would likely simplify the district court case. Finally, Petitioner argued that the strong merits of its unpatentability challenges weighed heavily against discretionary denial.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-17 of Patent 6,774,033 as unpatentable.