Microchip Technology Inc v. HD Silicon Solutions LLC

1. Case Identification

• Case #: IPR2021-00872
• Patent #: 7,302,619
• Filed: May 28, 2021
• Petitioner(s): Microchip Technology Inc.
• Patent Owner(s): HD Silicon Solutions LLC
• Challenged Claims: 1-32

2. Patent Overview

• Title: Error Correction in a Cache Memory
• Brief Description: The ’619 patent discloses systems and methods for correcting errors, such as single-bit flips caused by alpha particles, in instructions stored in an instruction cache that is coupled to a processor. The invention performs error detection and correction concurrently with instruction fetching operations.

3. Grounds for Unpatentability

Ground 1: Obviousness over Lempel and Itou - Claims 1-9 and 13-32 are obvious over Lempel in view of Itou.

• Prior Art Relied Upon: Lempel (Patent 7,290,179) and Itou (Patent 7,395,489).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that the combination of Lempel and Itou taught all limitations of the challenged claims. Lempel disclosed a system for handling "soft errors" in a cache memory, including an instruction cache coupled to a processor, and taught that error detection can occur while data is being fetched. This met the core limitations of fetching instructions and performing concurrent error detection. Itou, which is concerned with reducing memory access delays from data protection, disclosed a memory control circuit that executes error detection in parallel with a memory reading operation. Petitioner contended Itou’s disclosure of performing operations like an ECC check in a subsequent machine cycle (e.g., cycle XP2 after a read in cycle XP1) taught the limitations of performing actions across a "plurality of instruction cycles" and performing error detection concurrently with fetching. For dependent claims, Itou was cited for its teachings on generating a corrected instruction (claim 3), stalling the processor by issuing a "process cancel signal" (claim 5), and writing the corrected instruction back to memory (claim 6).
  • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine Lempel and Itou to create an improved error detection and recovery system. Both references address the same problem of errors in cache memory. A POSITA would integrate Itou’s efficient, ECC-based parallel processing method for correctable errors with Lempel’s methods for handling non-correctable errors (e.g., targeted invalidation) to achieve a more robust and faster solution. Itou’s method offered a clear speedup over Lempel’s, providing a strong incentive for its adoption.
  • Expectation of Success: The combination would have yielded predictable results. Both Lempel and Itou disclosed configurations using known hardware components and conventional error-correction principles, meaning their integration would not require substantial changes or present undue technical challenges.

Ground 2: Obviousness over Lempel, Itou, and Haswell - Claims 6-12, 17, 24, 25, 31, and 32 are obvious over Lempel in view of Itou and Haswell.

• Prior Art Relied Upon: Lempel (Patent 7,290,179), Itou (Patent 7,395,489), and Haswell (Patent 7,278,083).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground added Haswell to the combination of Lempel and Itou to further support the obviousness of various dependent claims related to specific error recovery actions. Haswell disclosed a method for optimized instruction fetch that protects against soft and hard errors. Petitioner asserted that Haswell explicitly taught writing a corrected instruction back into the instruction cache (SRAM 24) to replace the corrupted data, directly mapping to the limitation in claim 6. Furthermore, Haswell taught a mechanism for stalling the processor; when an error is detected, the transmission of corrupted data to the processor is stopped, and an interrupt is triggered for an error handling routine. During this routine, the processor does not execute instructions from the cache, which Petitioner argued constituted the claimed "stalling" (claim 9). Haswell also provided teachings on retrieving a correct instruction from main memory when an error is determined to be uncorrectable (claims 11 and 27).
  • Motivation to Combine: A POSITA would combine the teachings of all three references to create a comprehensive error-handling system. In the same spirit as the Lempel/Itou combination, a POSITA would incorporate Haswell’s teachings to implement faster and more specific error correction processes. Haswell provided an efficient method for handling correctable errors and stalling the processor, which would be a logical addition to the foundational system described by Lempel and the parallel processing improvements from Itou. All three references relate to the same field of error detection and correction in processor memory systems.
  • Expectation of Success: The combination of Lempel, Itou, and Haswell involved integrating well-understood hardware configurations and known error-handling techniques. A POSITA would have reasonably expected that combining these predictable elements would successfully result in an improved and more robust error correction system.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under §314(a) based on the Fintiv factors would be inappropriate. The petition was filed approximately six months after service of the complaint in a parallel district court litigation, leaving ample time before the statutory bar. Key arguments included:
  • The expected statutory deadline for a Final Written Decision (FWD) in the IPR (approximately November 2022) precedes the estimated trial date in the parallel litigation (December 5, 2022).
  • Investment in the district court proceeding had been minimal, as the petition was filed before claim construction and significant discovery had occurred.
  • The petition’s strong merits and its challenge to all 32 claims of the ’619 patent, including claims not asserted in the litigation, weigh in favor of institution to promote an efficient resolution.

5. Relief Requested

• Petitioner requested the institution of an inter partes review (IPR) and the cancellation of claims 1-32 of Patent 7,302,619 as unpatentable.