PTAB
IPR2021-00940
Micron Technology Inc v. Unification Technologies LLC
Key Events
Petition
Table of Contents
petition
1. Case Identification
- Case #: IPR2021-00940
- Patent #: 8,533,406
- Filed: June 4, 2021
- Petitioner(s): Micron Technology, Inc.; Micron Semiconductor Products, Inc.; and Micron Technology Texas LLC
- Patent Owner(s): Unification Technologies LLC
- Challenged Claims: 15-21, 26
2. Patent Overview
- Title: APPARATUS, SYSTEM, AND METHOD FOR IDENTIFYING DATA THAT IS NO LONGER IN USE
- Brief Description: The ’406 patent relates to an apparatus for managing data in nonvolatile storage, such as a solid-state drive (SSD). The system includes a request receiver module that receives an "indication" that a data structure has been deleted and a marking module that records that the corresponding data can be erased.
3. Grounds for Unpatentability
Ground 1: Claims 15, 21, and 26 are obvious over Shu, Shu’s Trim Proposals, and Ban.
- Prior Art Relied Upon: Shu (Patent 9,207,876), Shu’s Trim Proposals (public proposals to the T13 standards committee), and Ban (Patent 5,404,485).
- Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Shu teaches the core inventive concept: a host system sending a "remove-on-delete" command (functionally identical to the industry "Trim" command) to an SSD to improve efficiency. This command serves as the claimed "indication," specifies a "logical identifier" (a logical block address or LBA), and is sent by a "storage client" (the host file system). Upon receipt, the SSD’s "marking module" records that the data is invalid and "can be erased," preventing it from being preserved during garbage collection. Ban was cited for teaching the foundational architecture of an SSD, including a flash translation layer (FTL) that maps logical identifiers to physical addresses, which was the well-known context for Shu's invention. The Shu Trim Proposals were used to supplement Shu by providing explicit details on the Trim command format, confirming its use of LBAs.
- Motivation to Combine: Petitioner asserted that Shu provided an explicit motivation to combine its teachings with a conventional SSD architecture like that in Ban. Shu taught using its new command to improve the performance of existing solid-state devices. A person of ordinary skill in the art (POSITA) implementing Shu's command would have been motivated to consult the publicly available Shu Trim Proposals for details on the command's format to ensure compliance with the prevailing ATA industry standard.
- Expectation of Success: A POSITA would have had a high expectation of success in combining the references, as it involved applying a new software command to a well-understood hardware architecture (Ban) for the predictable result of improved data management efficiency, as taught by Shu.
Ground 2: Claims 16-20 are obvious over Shu, Shu’s Trim Proposals, Ban, and Jenett.
- Prior Art Relied Upon: Shu (Patent 9,207,876), Shu’s Trim Proposals, Ban (Patent 5,404,485), and Jenett (Patent 6,014,724).
- Core Argument for this Ground:
- Prior Art Mapping: This ground adds Jenett to the combination from Ground 1 to address the specific limitations of dependent claims 16-20, which recite particular methods of marking data invalid. Shu taught that marking could take "any form sufficient," creating a need for a specific implementation. Jenett was argued to disclose these specific methods as common techniques used by SSDs to manage invalid data. Specifically, Jenett taught invalidating data by "delet[ing] the association" or "remov[ing] a mapping" between the logical identifier and the physical address from an index or "block allocation map." Petitioner contended these teachings directly map to the limitations of claims 16-20.
- Motivation to Combine: A POSITA, tasked with implementing the general "marking" function described in Shu, would have been motivated to use a well-known and proven technique for doing so. Petitioner argued that Jenett provided such a technique, which was designed for the same type of SSD architecture and would have worked predictably within Shu's system. The combination represented a simple implementation of a known marking technique (Jenett) to carry out a step in Shu's broader data management process.
- Expectation of Success: Incorporating Jenett's well-established method for deleting mappings into Shu's system was presented as a straightforward design choice with a predictable outcome and a high expectation of success.
4. Key Technical Contentions (Beyond Claim Construction)
- Invalid Priority Claim: A central contention of the petition was that the ’406 patent is not entitled to the priority date of its 2006 provisional application. Petitioner argued the 2006 provisional lacks written description support for two key limitations of claim 15: (1) an "indication [that] comprises a logical identifier that is associated with the data structure by a storage client" and (2) a "marking module" configured to record that data "can be erased." Petitioner asserted this failure to meet the written description requirement under 35 U.S.C. §112 pushes the patent’s effective priority date to at least September 22, 2007, which critically renders the Shu Patent and Shu Trim Proposals (published in April and August 2007) intervening prior art.
5. Arguments Regarding Discretionary Denial
- Petitioner argued that discretionary denial would be inappropriate. The grounds presented were asserted not to be cumulative to the issues examined during prosecution because the Examiner was never presented with Frank Shu's Trim Proposals, which clarified the prior art "remove-on-delete" command that the Patent Owner now accuses of infringement. Petitioner also argued against denial based on a parallel IPR proceeding (IPR2021-00343), noting that the earlier petition assumed, without conceding, the 2006 priority date and thus relied on different prior art, making the grounds in this petition distinct.
6. Relief Requested
- Petitioner requests institution of an inter partes review and cancellation of claims 15-21 and 26 of Patent 8,533,406 as unpatentable.
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