PTAB

IPR2021-00967

NXP Semiconductors NV v. Bell Semiconductor LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Methods for Avoiding Parasitic Capacitance in an Integrated Circuit Package
  • Brief Description: The ’269 patent describes methods for manufacturing an integrated circuit (IC) package substrate. The methods focus on reducing parasitic capacitance between the substrate's electrical connection pads and internal metal layers by removing metal in layers adjacent to the pads, which is intended to improve performance in high-frequency applications like serializing/deserializing (SERDES) devices.

3. Grounds for Unpatentability

Ground 1: Obviousness over Chin - Claims 1 and 3-20 are obvious over Chin.

  • Prior Art Relied Upon: Chin (Patent 6,765,298).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Chin teaches a nearly identical solution to the same problem addressed by the ’269 patent: reducing parasitic capacitance on a package substrate. Chin discloses fabricating multi-layered substrates by forming alternating layers of metal and dielectric. Petitioner asserted that Chin teaches forming a first conductive layer with contact pads (inherently arranged in rows for a Ball Grid Array (BGA) package), an insulating layer, and a second conductive layer that includes "patterned holes" or cutouts. These cutouts are aligned with the contact pads, creating an insulating area that completely overlaps the pads, thereby achieving the claimed "substantially no overlap" of the contact pads with metal in the second layer. Petitioner contended that the dependent claims recite obvious design choices or common uses, such as using transmit/receive pads, employing routing or ground layers, and connecting the substrate to a printed circuit board, all of which were known in the art and suggested or disclosed by Chin. For claim 3, Petitioner argued that sizing the cutouts to have the same dimensions as the contact pads was an obvious design choice to balance shielding and routing flexibility.
    • Motivation to Combine (for §103 grounds): As this ground is based on a single reference, the motivation was framed as a POSITA’s incentive to apply Chin's teachings directly. Petitioner argued a POSITA would have recognized that Chin’s method of using patterned holes to reduce parasitic capacitance was directly applicable to designing integrated circuit packages.
    • Expectation of Success (for §103 grounds): A POSITA would have had a high expectation of success in applying Chin's methods, as Chin explicitly addresses the same technical problem of parasitic capacitance and provides a detailed methodology for its reduction using conventional fabrication techniques.

Ground 2: Obviousness over Chin and HighSpeed - Claims 5, 8, 14-16, and 19 are obvious over Chin in view of HighSpeed.

  • Prior Art Relied Upon: Chin (Patent 6,765,298) and HighSpeed (a 2000 textbook on digital system design).

  • Core Argument for this Ground:

    • Prior Art Mapping: This ground supplements Chin with HighSpeed to provide additional support for dependent claims requiring specific layer arrangements. Petitioner argued that Chin discloses the fundamental structure of using cutouts to reduce capacitance. HighSpeed, a widely known reference book, demonstrates a POSITA's knowledge of common high-speed design techniques, including arranging a routing layer immediately adjacent to a contact pad layer and connecting them with vias. This combination was asserted to teach the limitations of claims 5 and 8, which require forming certain conductive layers as routing layers and ground plane layers.
    • Motivation to Combine (for §103 grounds): A POSITA, seeking to implement Chin's capacitance-reduction technique in a multi-layer BGA package for high-speed signals, would be motivated to look to established design principles for arranging routing and ground layers, as detailed in HighSpeed. Both references address the same field of endeavor—high-speed IC package design—making the combination logical and intuitive for improving signal integrity.
    • Expectation of Success (for §103 grounds): A POSITA would expect success in combining the teachings, as it involves applying a known routing configuration (from HighSpeed) to a known substrate structure (from Chin) to achieve the predictable result of a functional, high-performance package with reduced parasitic capacitance.

  • Additional Grounds: Petitioner asserted additional obviousness challenges for claim 2 over Chin in view of MC92600 (a SERDES reference manual) and over Chin in view of Shafer (Patent 6,908,340). Petitioner also challenged claim 3 over Chin in view of Oggioni (Patent 6,717,255). These grounds relied on similar theories of combining Chin's primary teachings with specific features disclosed in the secondary references, such as SERDES functionality, transmit/receive row arrangements, or same-sized cutouts.

4. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under Fintiv is unwarranted because the petition was filed with a motion for joinder to an already-instituted proceeding (IPR2021-00147), obviating concerns of serial petitions. Petitioner contended that Fintiv factors weigh against denial because: (1) substantial work remains in the parallel district court litigation; (2) Petitioner stipulated not to pursue in the district court any ground raised or that could have been reasonably raised in the IPR; and (3) the unpatentability grounds are strong, as evidenced by the institution of the parallel IPR.

5. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-20 of the ’269 patent as unpatentable.