Microchip Technology Inc v. HD Silicon Solutions LLC

1. Case Identification

• Case #: IPR2021-01042
• Patent #: 7,302,619
• Filed: June 15, 2021
• Petitioner(s): Microchip Technology Inc.
• Patent Owner(s): HD Silicon Solutions LLC
• Challenged Claims: 1-32

2. Patent Overview

• Title: Error Correction in a Cache Memory
• Brief Description: The ’619 patent discloses systems and methods for correcting errors in instructions stored in an instruction cache coupled to a processor. The invention aims to minimize processor instruction cycle delays by performing error detection and correction functions concurrently with instruction fetch operations.

3. Grounds for Unpatentability

Ground 1: Anticipation and Obviousness over Haswell - Claims 1, 10, 11, 13, 21, 22, 24, 26, and 29-31 are anticipated by or obvious over Haswell.

• Prior Art Relied Upon: Haswell (Patent 7,278,083).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Haswell, which discloses a method for detecting and correcting errors in instructions transferred from an instruction cache (SRAM 24) to a processor (CPU 12), teaches every limitation of the independent claims. Specifically, Haswell’s instruction side on-chip memory (I-OCM) unit fetches instructions for the processor during timed clock cycles. Petitioner asserted that Haswell explicitly discloses performing error checking "simultaneously with the commencement of transmission of the raw data signal from the data memory to the computer processor," which meets the core limitation of performing error detection concurrently with fetching an instruction. The arguments for system claims 21 and 29 mirrored the method claim arguments, identifying Haswell's ECC GEN/CK unit 26 as the claimed "circuitry" or "means for" performing the concurrent error detection.
  • Key Aspects: The argument centered on Haswell’s disclosure of performing the fetch and error check for the same instruction within a single clock cycle, directly mapping to the concurrent operation described in the ’619 patent.

Ground 2: Obviousness over Haswell and Itou - Claims 2-9, 14-20, 23-25, 27, and 32 are obvious over Haswell in view of Itou.

• Prior Art Relied Upon: Haswell (Patent 7,278,083) and Itou (Patent 7,395,489).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Haswell provides the foundational system of a processor-coupled cache with error correction, while Itou teaches modifications to the timing of error detection. Itou discloses a memory control circuit where error detection (e.g., an ECC check) is performed in a clock cycle subsequent to the cycle in which the instruction is fetched. For example, Itou teaches fetching data during a first cycle (XP1) and performing the ECC check during a second cycle (XP2). This addresses limitations in dependent claims (e.g., claim 2) that require error detection to occur in a cycle subsequent to the fetch cycle. Itou further discloses stalling the processor upon error detection and writing the corrected instruction back to the cache, mapping to other dependent claims.
  • Motivation to Combine: A POSITA would combine these references to leverage different ECC-based options for error handling. Haswell’s concurrent method is efficient, but Itou’s sequential method (fetch then check) could enable a faster clock speed (i.e., a shorter clock period) by separating these operations, which would have been a known design trade-off. A POSITA would have been motivated to combine these known techniques to optimize performance based on system needs.
  • Expectation of Success: The combination involved applying Itou's known timing-based error detection method to Haswell's standard cache architecture. As both references use well-understood ECC principles and hardware components, a POSITA would have reasonably expected the combined system to function predictably.

Ground 3: Obviousness over Haswell and Lempel - Claims 12 and 28 are obvious over Haswell in view of Lempel.

• Prior Art Relied Upon: Haswell (Patent 7,278,083) and Lempel (Patent 7,290,179).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground built upon Haswell’s disclosure of detecting an uncorrectable error (as established in Ground 1 for claim 10). Lempel was introduced to teach the specific technique of "mimicking a cache miss condition" to handle such an error. Lempel discloses that when a soft error is detected, the cache line can be invalidated or cleared. This forces a "cache miss" on a subsequent fetch, which in turn causes the cache line to be reloaded with a correct version of the instruction from main memory. This directly teaches the primary limitation of claims 12 and 28.
  • Motivation to Combine: A POSITA would combine Haswell and Lempel to create a more robust error handling system. A designer would use Haswell’s efficient ECC-based method for common, correctable single-bit errors. For rarer, non-correctable errors, the designer would look to known solutions like Lempel’s, which uses the existing cache miss mechanism to refresh the data from main memory. This combination represents a logical integration of two known solutions for two different types of errors (correctable vs. non-correctable).
  • Expectation of Success: Integrating Lempel's cache-miss-based error recovery into Haswell's system would be straightforward for a POSITA. The use of cache miss protocols to reload data was a fundamental aspect of cache design, ensuring a high expectation of success.

4. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under §314(a) and the Fintiv factors was inappropriate. The estimated trial date in the parallel district court litigation (December 5, 2022) was close to or after the statutory deadline for a Final Written Decision (FWD), and such dates are often delayed. Furthermore, Petitioner asserted it filed the petition early in the litigation timeline, before significant investment by the court, and that the petition presented strong grounds for invalidity, all of which weigh against discretionary denial.

5. Relief Requested

• Petitioner requested institution of an inter partes review and cancellation of claims 1-32 of the ’619 patent as unpatentable.