PTAB

IPR2021-01104

Intel Corp v. Acqis LLC

Key Events

Petition

petition

Title: Computer System with Attached Module and Peripheral Console
Brief Description: The ’797 patent discloses a modular computer architecture featuring a primary processing unit, the "attached computer module" (ACM), and a "peripheral console" (PCON). The ACM contains core components like the CPU and graphics subsystem, and communicates with peripherals in the PCON via a high-speed serial interface known as the XPBus, which utilizes Low-Voltage Differential Signaling (LVDS) channels.

Prior Art Relied Upon: Chu330 (Patent 6,345,330) and Cupps (Application # 2003/0135771).
Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Chu330 discloses a nearly identical modular computer architecture to the ’797 patent, including an ACM, a PCON, and an XPBus interface for communication between them. Cupps was presented as teaching the well-known practice and benefits of integrating a CPU, graphics controller, and interface controller onto a single chip. The challenged claims, particularly those requiring an "integrated CPU and graphics controller chip," were alleged to be a straightforward application of Cupps’s teachings to Chu330’s system.
- Motivation to Combine: A POSITA would combine the teachings to achieve predictable improvements widely sought in the field, such as reduced power consumption, increased performance, and a smaller physical footprint. Cupps explicitly taught these benefits of integration, and Chu330 identified low power consumption as a design goal, providing clear motivation for the combination.
- Expectation of Success: Petitioner asserted a high expectation of success, as the components described in Chu330 (CPU, graphics subsystem, host interface controller) are functionally analogous to the components (processor, graphics controller, I/O controller) that Cupps teaches are commonly integrated onto a single chip.

Prior Art Relied Upon: Chu330 (Patent 6,345,330), Cupps (Application # 2003/0135771), and Helms (Patent 7,146,510).
Core Argument for this Ground:
- Prior Art Mapping: This ground builds upon the combination of Chu330 and Cupps from Ground 1. Helms was introduced to teach a Phase-Locked Loop (PLL) clock circuit that generates multiple, selectable clock frequencies for an I/O interface. This allows for adjusting data transfer rates. Petitioner contended that this addresses the limitation in claim 38 of configuring an interface controller to generate different data transfer frequencies based on different clock frequencies from a PLL.
- Motivation to Combine: A POSITA would incorporate Helms’s adjustable frequency PLL into the integrated Chu330/Cupps system to enhance power management and system flexibility. Helms teaches that adjusting link frequency provides power management capabilities, and Chu330’s desire for low power consumption would have motivated this addition.
- Expectation of Success: Helms demonstrated that implementing an interface controller to convey data at different clock frequencies was a known technique for interfaces substantially similar to the one in Chu330, ensuring a reasonable expectation of success.

Prior Art Relied Upon: Chu330 (Patent 6,345,330), Cupps (Application # 2003/0135771), and Chu777 (Patent 6,643,777).
Core Argument for this Ground:
- Prior Art Mapping: This ground also builds on the Chu330 and Cupps combination. Chu777, from the same inventor as the ’797 patent, was added for its teachings on using flash memory as a mass storage device and adding Ethernet support via a network card. This allegedly renders obvious the dependent claims requiring flash memory and Ethernet communication support.
- Motivation to Combine: Petitioner argued that Chu777 provides an express teaching that a hard disk drive (as disclosed in Chu330) can be replaced with flash memory, making it a simple substitution of one known element for another. Adding Ethernet was a routine and desirable enhancement for any computer system to provide network connectivity.
- Expectation of Success: The proposed modifications were characterized as standard, well-understood design choices in computer architecture at the time, leading to a high expectation of successfully integrating these features into the Chu330/Cupps system to yield predictable results.

Petitioner dedicated a significant portion of the petition to arguing that the ’797 patent is not entitled to a priority date earlier than April 15, 2011. The argument asserted that key claim limitations related to an "integrated CPU" and "CPU-LVDS" channels were not supported by the parent applications. Petitioner contended this subject matter constituted new matter first introduced in the application for the ’436 patent and was not properly incorporated by reference from the earlier ’886 provisional application. This later priority date is critical, as it makes references like Cupps and Helms available as prior art.

§325(d) Prosecution History: Petitioner argued that denial would be inappropriate because the Examiner did not previously consider the most relevant art or arguments. Specifically, the Examiner never considered Cupps or Helms and, critically, did not properly determine the correct (later) priority date for the challenged claims, which was necessary to evaluate the art correctly.
§314(a) Fintiv Factors: Petitioner argued that the Fintiv factors weigh in favor of institution. The petition noted that Intel itself is not a party to the parallel district court litigations. While certain Real Parties-in-Interest (RPIs) are defendants, the litigation was argued to be at an early stage, with claim construction and significant discovery yet to occur. Furthermore, the RPIs expressed willingness to stipulate not to pursue the same invalidity grounds in district court if the IPR is instituted, mitigating concerns of duplicative efforts.

Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 4-6, 14-17, and 27-38 of Patent 8,977,797 as unpatentable.