Intel Corp v. Acqis LLC

1. Case Identification

• Case #: IPR2021-01107
• Patent #: 9,529,768
• Filed: June 14, 2021
• Petitioner(s): Intel Corporation
• Patent Owner(s): Acqis LLC
• Challenged Claims: 4-6, 10-12

2. Patent Overview

• Title: Computer System with Attached Computer Module and Peripheral Console
• Brief Description: The ’768 patent describes a modular computer architecture comprising a removable attached computer module (ACM) containing core processing components and a peripheral console (PCON) with I/O devices, interconnected via a high-speed interface.

3. Grounds for Unpatentability

Ground 1: Claims 4-6 are obvious over Chu330 in view of Peleg and Helms.

• Prior Art Relied Upon: Chu330 (Patent 6,345,330), Peleg (Patent 6,557,065), and Helms (Patent 7,146,510).
• Core Argument for this Ground:
  • Prior Art Mapping: Petitioner argued that Chu330 discloses a base modular computer system with a Host Interface Controller (HIC) and Peripheral Interface Controller (PIC) connecting a notebook PC to a docking station via a low pin count, high-speed serial bus (XPBus). However, Chu330’s standard architecture includes an intervening PCI bus between the CPU and the peripheral bridge (South Bridge). Peleg teaches a highly integrated architecture where the CPU/Northbridge is directly coupled to the Southbridge via a front-side bus, disclosing the claimed direct coupling without an intervening PCI bus. Helms discloses an I/O Hub that combines the functionality of a Southbridge and an interface controller (like Chu330's HIC) into a single integrated chip, as required by claim 4. The combination of these references allegedly renders every limitation of independent claim 4 obvious.
  • Motivation to Combine: A POSITA would combine Chu330’s modular design with Peleg’s improved, high-speed architecture to obtain the benefits of both portability and performance. It was a known design goal to increase integration to reduce system size, cost, and power consumption. A POSITA would therefore be motivated to further integrate the Southbridge from the combined Chu330/Peleg system with the interface controller functionality using the single-chip I/O Hub taught by Helms to achieve these predictable benefits.
  • Expectation of Success: A POSITA would have a reasonable expectation of success because integrating known computer components like a Southbridge and an interface controller was a common practice to achieve well-understood benefits in performance and power efficiency.

Ground 2: Claims 10-12 are obvious over Chu330 in view of Peleg, Helms, and Chu8415.

• Prior Art Relied Upon: Chu330 (Patent 6,345,330), Peleg (Patent 6,557,065), Helms (Patent 7,146,510), and Chu8415 (Patent 6,718,415).
• Core Argument for this Ground:
  • Prior Art Mapping: This ground builds upon the combination asserted in Ground 1. The primary combination of Chu330, Peleg, and Helms is argued to teach the core limitations of independent claim 10, including the printed circuit board, CPU, and a peripheral bridge directly coupled to the CPU. The additional reference, Chu8415, is introduced to teach the final limitation: "a network controller coupled to the central processing unit." Chu8415 explicitly discloses a modular computer system with an Ethernet network controller (e.g., Intel 82559) coupled to the North Bridge via a PCI bus, thereby being coupled to the CPU.
  • Motivation to Combine: A POSITA would be motivated to add the network controller from Chu8415 to the base system of Chu330/Peleg/Helms to provide desirable, high-speed networking capabilities. Petitioner argued that adding network functionality was a common and obvious improvement for computer systems at the time, and Chu8415 shows a standard way of implementing it. The inclusion of high-performance components like a network controller in the core computer module was taught as advantageous in the art incorporated by Chu330 itself.
  • Expectation of Success: Success would be expected, as adding a well-known component like an Intel 82559 network controller to a motherboard with a PCI bus was a routine, well-understood task for a POSITA.

4. Key Claim Construction Positions

• "peripheral bridge": Petitioner argued this term should be construed as "a south bridge that interfaces with a peripheral bus or device." This construction is based on the ’768 patent’s specification, which consistently identifies the "peripheral bridge" as a "South Bridge" and distinguishes it from the "CPU Bridge," which is identified as the "North Bridge." This distinction is central to Petitioner’s argument that the claims require a direct CPU-to-Southbridge connection, a feature allegedly taught by Peleg but not the primary reference Chu330.

5. Key Technical Contentions (Beyond Claim Construction)

• Priority Date Challenge: Petitioner dedicated significant argument to establishing that the challenged claims are not entitled to a priority date earlier than April 15, 2011, the filing date of the ’436 patent. Petitioner contended that the key limitation requiring a "peripheral bridge...directly coupled to the [CPU] without any intervening PCI bus" was first introduced in the ’436 patent and constitutes new matter not supported by any of the preceding parent applications. The argument asserted that the earlier applications failed to properly incorporate by reference a provisional application (’886 Provisional) that allegedly contained support for this feature. Therefore, key prior art references like Peleg and Helms, which predate 2011, are available to be cited against the claims.

6. Arguments Regarding Discretionary Denial

• Petitioner argued that discretionary denial under either 35 U.S.C. §325(d) or the Fintiv factors would be inappropriate.
• §325(d): Petitioner asserted that while the primary reference Chu330 was listed in an IDS, it was never applied by the Examiner. More importantly, the Examiner never considered the key secondary references (Peleg, Helms) and failed to correctly determine the claims' proper priority date, which was a material error that allowed the claims to issue.
• Fintiv Factors: Petitioner argued that the factors weigh against denial because the parallel district court cases are at an early stage, with discovery stayed and claim construction yet to occur. Further, Petitioner Intel Corporation is not a defendant in the parallel litigations, and the Real Parties-in-Interest that are defendants are willing to stipulate not to pursue the same invalidity grounds in district court, mitigating concerns of duplicative efforts.

7. Relief Requested

• Petitioner requests institution of an inter partes review and cancellation of claims 4-6 and 10-12 of the ’768 patent as unpatentable under 35 U.S.C. §103.