PTAB

IPR2021-01212

Siemens Industry Software Inc v. Synopsys Inc

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1. Case Identification

2. Patent Overview

  • Title: Method and Apparatus for Generating a Variation-Tolerant Clock-Tree for an Integrated Circuit Chip
  • Brief Description: The ’567 patent discloses a method for clock-tree synthesis in an integrated circuit. The method involves clustering registers based on their timing constraints to maximize commonly-shared clock paths, thereby making the clock-tree more tolerant to on-chip variations.

3. Grounds for Unpatentability

Ground 1: Obviousness over Sano - Claims 1-8, 11-20, and 23-25 are obvious over Sano.

  • Prior Art Relied Upon: Sano (Patent 6,651,224).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Sano discloses a method for creating a clock-tree that meets all limitations of the challenged claims. Sano’s process begins with a chip layout containing flip-flops (registers) at fixed locations. It then calculates "evaluation values" for pairs of flip-flops, which indicate the probability of a timing setup error and function as the claimed "timing criticality." Sano then groups (clusters) the flip-flops based on these evaluation values, prioritizing pairs with the "largest evaluation value" first. This timing-based clustering facilitates the use of commonly-shared clock paths to suppress setup errors for these timing-critical pairs, resulting in a completed clock-tree.
    • Motivation to Combine (for §103 grounds): This ground relied on a single reference. Petitioner asserted that Sano alone teaches every element of the claims. The petition argued that Sano's first embodiment, focused on timing-based clustering, and its fourth embodiment, a more general IC design process using floorplan information, could be obviously combined as Sano itself suggests combining embodiments. A POSITA would have incorporated the specific timing-based clustering from the first embodiment into the general design flow of the fourth embodiment to gain the stated benefits of setup error prevention.
    • Expectation of Success (for §103 grounds): A POSITA would have had a high expectation of success as Sano explicitly describes the benefits of its timing-based clustering for improving circuit quality.

Ground 2: Obviousness over Cheng - Claims 1-7, 11-19, and 23-25 are obvious over Cheng.

  • Prior Art Relied Upon: Cheng (Patent 6,367,060).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner contended that Cheng discloses a multi-step clock tree synthesis process that renders the claims obvious. The process begins by receiving placement information for registers. It then performs an initial bottom-up clustering to create a clock tree. Subsequently, Cheng extracts timing information and tests for setup/hold time violations for register pairs, which Petitioner equated to generating a timing criticality profile. Based on these timing violations, Cheng re-clusters the register pairs by, for example, swapping registers between clusters to increase the number of shared buffers and correct the violations.
    • Motivation to Combine (for §103 grounds): This ground relied primarily on a single reference with an obvious modification. While Cheng did not explicitly state the order for correcting multiple timing violations, Petitioner argued a POSITA would have been motivated to address the violations sequentially, based on severity. This priority-based ordering was a known technique to address on-chip variations and would have been an obvious way to optimize the performance and yield of the clock tree by addressing the most adverse violations first.
    • Expectation of Success (for §103 grounds): A POSITA would have reasonably expected success, as this modification only involved applying a known, priority-based clustering approach to the order of operations in Cheng’s disclosed method.

Ground 3: Obviousness over Cheng and Sherwani - Claims 4, 8, 16, and 20 are obvious over Cheng in view of Sherwani.

  • Prior Art Relied Upon: Cheng (Patent 6,367,060) and Sherwani (a 1999 textbook, "Algorithms for VLSI Physical Design Automation").
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon Ground 2, adding Sherwani to explicitly teach the "geometric location-based clustering process" recited in claims 8 and 20. Cheng’s initial clustering step (before the timing-violation-based re-clustering) allows for "any number of techniques." Sherwani, a well-known textbook, teaches a "Geometric Matching Algorithm" that clusters registers based on physical proximity to reduce clock skew. The combination of Cheng's overall process with Sherwani's geometric clustering for the initial step disclosed the two-stage clustering process of claims 8 and 20.
    • Motivation to Combine (for §103 grounds): A POSITA implementing Cheng's method would have naturally turned to well-known techniques, like those in the Sherwani textbook, for the initial clustering step. Sherwani’s geometric algorithm was a clear design choice that was known to reduce clock skew, providing a direct motivation for its use in Cheng's process.
    • Expectation of Success (for §103 grounds): Success was expected, as this combination involved implementing a well-known, conventional clustering algorithm within the flexible framework disclosed by Cheng.

4. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under §325(d) would be improper because the primary prior art references, Sano and Sherwani, were never considered by the examiner during prosecution. Petitioner further argued that while Cheng was listed on an IDS, it was not substantively considered in a manner material to patentability, and thus the examiner erred.
  • Petitioner also argued against discretionary denial under Fintiv. It asserted that the parallel district court litigation was likely to be stayed pending arbitration before the institution of the inter partes review (IPR). Because a trial would likely occur after a Final Written Decision (FWD) from the Board, the Fintiv factors weighed against denial.

5. Relief Requested

  • Petitioner requested institution of an IPR and cancellation of claims 1-8, 11-20, and 23-25 of the ’567 patent as unpatentable.