PTAB

IPR2021-01215

Siemens Industry Software Inc v. Synopsys Inc

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Key Events
Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Fixing Design Requirement Violations in Multiple Multi-Corner Multi-Mode Scenarios
  • Brief Description: The ’655 patent discloses a method for expediting the validation of Engineering Change Orders (ECOs) in integrated circuit design. The method avoids sequentially loading large databases for multiple operating scenarios by loading a single "scenario image" and a smaller "multi-scenario ECO database," then estimating any missing parameter values needed to check for new violations across all scenarios.

3. Grounds for Unpatentability

Ground 1: Anticipation and Obviousness over Yoshimura - Claims 1-24 are anticipated by or obvious over Yoshimura.

  • Prior Art Relied Upon: Yoshimura (Patent 7,464,355).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Yoshimura discloses every limitation of the challenged claims. Like the ’655 patent, Yoshimura addresses the inefficiency of validating ECOs by iteratively checking each scenario ("corner"). It teaches a similar solution: expediting the process by estimating parameter values for some scenarios based on known values from other scenarios. Petitioner asserted Yoshimura's "timing list 12" and "slack file 13" constitute the claimed "scenario image," and its "libraries 11a,b" constitute the "multi-scenario ECO database." The process of recalculating path delay and slack in step S5 of Yoshimura, based on data from both the scenario image and the multi-scenario database, was mapped to the claimed step of "estimating parameter values."
    • Motivation to Combine (for §103 grounds): To the extent any claim limitations were not explicitly disclosed, Petitioner argued they would have been obvious modifications. For example, using specific parameter values (e.g., capacitive load, leakage power) or checking for specific violations (e.g., setup time, electrical design rules) not detailed in Yoshimura were well-known and standard in the art. A POSITA would have been motivated to incorporate these standard checks into Yoshimura’s framework to ensure the overall proper functioning of the circuit design.
    • Expectation of Success (for §103 grounds): A POSITA would have had a high expectation of success because implementing these well-known parameter types and violation checks into Yoshimura's existing multi-scenario analysis framework represented a straightforward application of conventional techniques to achieve a predictable result.

Ground 2: Obviousness over Yoshimura in view of Scheffer - Claims 4-7, 9-10, 14-17, 19-20, and 23-24 are obvious over Yoshimura in view of Scheffer.

  • Prior Art Relied Upon: Yoshimura (Patent 7,464,355) and Scheffer (EDA FOR IC IMPLEMENTATION, CIRCUIT DESIGN, AND PROCESS TECHNOLOGY, 2006).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground augmented the Yoshimura reference to address claims reciting specific parameter values and design violations. Petitioner argued that Yoshimura provides the foundational framework for multi-scenario ECO validation with parameter estimation. Scheffer, a standard industry handbook, was cited to demonstrate that the specific parameter values recited in claims 4-6 (capacitive load, transition time, leakage power) and the specific design violations in claims 7, 9-10 (setup timing, electrical design rule, power budget) were all well-known concepts in the art of circuit design and analysis before the ’655 patent’s priority date.
    • Motivation to Combine (for §103 grounds): A POSITA would combine Scheffer’s teachings with Yoshimura’s system to improve its robustness and ensure circuit viability. Since Yoshimura’s goal was to validate ECOs, a POSITA would naturally be motivated to incorporate the standard and critical checks described in Scheffer (e.g., for power, noise, and setup timing) to create a more comprehensive and effective validation tool. Scheffer provided the known inputs (parameter values) and criteria (design rules) necessary for such a tool.
    • Expectation of Success (for §103 grounds): Success was expected because the combination merely involved applying conventional analysis techniques and parameters, as detailed in the Scheffer handbook, to the known ECO validation framework taught by Yoshimura. This constituted the application of known techniques to a known system to yield predictable results.

Ground 3: Obviousness over Srinivas - Claims 1-24 are obvious over Srinivas.

  • Prior Art Relied Upon: Srinivas (Patent 7,092,838).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner contended that Srinivas teaches an efficient method for analyzing circuit performance across multiple corners and modes simultaneously, avoiding the inefficient iterative approach criticized by the ’655 patent. Srinivas discloses generating performance data across all scenarios but storing only a subset to reduce memory overhead, which Petitioner mapped to the claimed "multi-scenario ECO database." Srinivas explicitly teaches "re-computing" eliminated data when needed from other stored data, which directly corresponds to the ’655 patent’s concept of "estimating parameter values." The circuit graph and its associated matrices in Srinivas, which store performance data, were argued to meet the limitations of the "scenario image."
    • Motivation to Combine (for §103 grounds): Although Petitioner argued Srinivas teaches all limitations, it asserted in the alternative that any minor variations would have been obvious. For example, separating the stored data into two distinct databases (scenario image and multi-scenario ECO database) as construed by the district court was presented as a simple, obvious design choice for organizing data.
    • Expectation of Success (for §103 grounds): A POSITA would have reasonably expected success in implementing the claimed method based on Srinivas, as Srinivas already provided a complete framework for multi-scenario analysis with on-the-fly data re-computation to fix design violations.
  • Additional Grounds: Petitioner asserted an additional obviousness challenge against claims 6, 9-10, 16, and 19-20 based on Srinivas in view of Scheffer, relying on similar theories for incorporating Scheffer’s well-known teachings.

4. Key Claim Construction Positions

  • For purposes of the IPR, Petitioner adopted several of Patent Owner's proposed constructions from parallel litigation. The constructions for two terms central to the petition were:
  • "scenario image": "information required to detect and/or fix design requirement violations in a circuit design in a particular scenario." This construction was argued to be met by the prior art's disclosure of files containing timing and slack data (Yoshimura) or circuit graphs with performance data matrices (Srinivas).
  • "multi-scenario ... ECO database": "[A] database separate from the scenario image, containing circuit information for multiple scenarios." Petitioner argued this was met by Yoshimura’s libraries and that splitting Srinivas’s data into a separate database would be an obvious design choice.

5. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under Fintiv would be inappropriate. It stated that the parallel district court litigation was likely to be stayed pending arbitration of a related license dispute. Because the stay would likely be in place before an institution decision and a trial would occur well after a Final Written Decision (FWD), Petitioner contended that an IPR would be a more efficient resolution and would not be duplicative of court efforts.

6. Relief Requested

  • Petitioner requests institution of inter partes review of claims 1-24 and cancellation of those claims as unpatentable.