PTAB

IPR2021-01330

Intel Corp v. StreamScale Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: System for Accelerated Error-Correcting Code Processing
  • Brief Description: The ’296 patent discloses a system for accelerating erasure coding operations, such as Reed-Solomon coding. The invention purports to improve computational performance by using a "parallel multiplier" to concurrently multiply multiple data elements and a "sequencer" to order matrix operations for improved efficiency.

3. Grounds for Unpatentability

Ground 1: Obviousness over Macy, Li, and Plank - Claims 1-12 and 14-17 are obvious over Macy in view of Li, and further in view of Plank.

  • Prior Art Relied Upon: Macy (Patent 7,343,389), Li ("Parallelized Network Coding With SIMD Instruction Sets," a 2008 publication), and Plank ("A Tutorial on Reed-Solomon Coding for Fault-Tolerance in RAID-like Systems," a 1997 technical report).
  • Core Argument for this Ground:

    • Prior Art Mapping: Petitioner asserted that Macy, the primary reference, discloses the core elements of the claimed invention. Macy teaches a system for accelerated error control coding that performs matrix multiplication by multiplying a data matrix with an encoding matrix to generate a check matrix. Critically, Macy discloses accelerating this process using both a "parallel multiplier" implemented with Single Instruction, Multiple Data (SIMD) instructions (including PSHUFB, the same instruction used in the ’296 patent’s preferred embodiment) and a "sequencer" for selecting between different data access patterns (e.g., "horizontal" or "vertical") to improve efficiency. This combination, Petitioner argued, meets the central limitations of independent claim 1.

    • To meet the "thread for executing" limitation of claim 1 and limitations in dependent claims related to multi-core and multi-threaded processing, Petitioner relied on Li. Li describes accelerating matrix-based network coding using the same PSHUFB instruction and explicitly analyzes the performance trade-offs between single-threaded and multi-threaded implementations on multi-core processors.

    • To the extent Patent Owner might argue Macy’s "error control" is not "erasure coding," Petitioner relied on Plank. Plank is a foundational tutorial on Reed-Solomon erasure coding for RAID systems, disclosing the use of data, encoding, check, and solution matrices for both encoding data and decoding to recover lost data. Petitioner argued that combining Plank with Macy’s system provides explicit teachings on erasure coding and data recovery. For example, Plank’s disclosure of a solution matrix for data recovery was mapped to limitations in claims 7-11.

    • Motivation to Combine: Petitioner argued a person of ordinary skill in the art (POSITA) would combine Macy with Plank because both address improving storage systems like RAID. Macy proposes using its accelerated multiplication for data recovery in RAID systems but lacks specific implementation details, which Plank’s well-known tutorial provides. The combination would use a known technique (Plank’s erasure coding) to improve a similar system (Macy’s processing architecture) for its intended purpose.

    • A POSITA would combine the teachings of Li with Macy/Plank because they are in the same field of accelerating coding algorithms using SIMD instructions. Li’s direct comparison of single- and multi-threaded performance would have motivated a POSITA to apply this known optimization technique to the Macy/Plank system to achieve predictable performance gains depending on the specific coding conditions (e.g., data block size).

    • Expectation of Success: A POSITA would have had a reasonable expectation of success. The combination involves applying known optimization techniques (multi-threading from Li) and standard algorithms (erasure coding from Plank) to a compatible base system (Macy's accelerated processor). Since all references rely on accelerating standard matrix multiplication over Galois Fields, the integration would be straightforward and the results predictable.

4. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under Fintiv would be inappropriate. The petition was filed expeditiously, just eight months after the initial complaint was served. The parallel district court case was in its early stages, with no Markman hearing held, no trial date set, and a trial unlikely before May 2023. Petitioner also stipulated it would not assert the same invalidity grounds in the district court, mitigating concerns of duplicative efforts. Finally, Petitioner asserted the merits of the petition are particularly strong, which weighs in favor of institution.

5. Relief Requested

  • Petitioner requests institution of an inter partes review (IPR) and cancellation of claims 1-12 and 14-17 of the ’296 patent as unpatentable.