PTAB

IPR2021-01420

Microchip Technology Inc v. HD Silicon Solutions LLC

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: Saving Power When in or Transitioning to a Static Mode of a Processor
  • Brief Description: The ’731 patent is directed to methods for decreasing static power consumption in a processor. The methods involve reducing the processor's core voltage to a level sufficient to maintain state, but not processing activity, when the system clock is disabled.

3. Grounds for Unpatentability

Ground 1: Obviousness over NEC-Databook and Burd - Claims 1, 3, 6, and 7 are obvious over NEC-Databook in view of Burd.

  • Prior Art Relied Upon: NEC-Databook (a 1990 single-chip microcomputer databook) and Burd (a 2000 IEEE technical paper on a dynamic voltage scaled microprocessor system).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that NEC-Databook disclosed a processor with a "standby mode" that includes a "Data Retention mode" where the system clock is stopped and the supply voltage is lowered to 2V to reduce static power consumption while retaining the contents of RAM and registers (claim 1[a], 1[b]). This reduced voltage was insufficient for normal processing activity. Petitioner asserted that Burd disclosed a switching voltage regulator with two distinct modes: a "regulation mode" (corresponding to the ’731 patent's "high efficiency" mode) and a "tracking mode" (corresponding to the "continuous" mode). The regulator transitions between these modes to adjust its output voltage, such as during a high-to-low voltage transition. Specifically, Burd taught that in the tracking mode, the converter removes charge from the output capacitor and returns it to the input supply, thereby saving power compared to dissipating it in the regulation mode (claim 1[c], 1[c.1], 1[c.2]). Claim 3’s limitation of furnishing an input to reduce voltage was met by Burd’s “voltage scheduler” which provides a desired frequency input to the regulator to control its output voltage.
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine these references as they both address power optimization techniques for processors. A POSITA would have recognized that Burd’s adjustable voltage regulator provided a well-known and suitable component to implement the dynamic voltage changes required for the power-saving modes described in NEC-Databook. This combination was a simple substitution of one known voltage regulator for another to achieve the predictable benefit of reduced power consumption.
    • Expectation of Success: A POSITA would have had a high expectation of success as the combination involved applying a known voltage regulation technique (Burd) to a known processor with established power-saving states (NEC-Databook) to achieve a predictable improvement in power efficiency.

Ground 2: Obviousness over NEC-Databook, Burd, and Nguyen - Claim 2 is obvious over NEC-Databook in view of Burd, further in view of Nguyen.

  • Prior Art Relied Upon: NEC-Databook, Burd, and Nguyen (Patent 5,955,871).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground built upon the combination in Ground 1 to address the additional limitation of claim 2: "monitoring a stop clock signal" to determine the processor is transitioning to a disabled-clock mode. Petitioner argued that Nguyen disclosed this exact feature, teaching the use of a "STP_CLK#" signal to indicate a "power conservation mode" in which the processor clock is stopped. Nguyen's STP_CLK# signal directly controlled the operation of a voltage regulator, providing a clear implementation for the claimed "monitoring" step.
    • Motivation to Combine: A POSITA, seeking to implement the power-saving system of NEC-Databook and Burd, would have looked to known methods for signaling state transitions. Nguyen provided a straightforward and common solution: a dedicated "stop clock" signal. Using such a signal was a simple and predictable design choice to trigger the voltage reduction in the combined system, offering a more direct control mechanism than inferring the state from other processor outputs.

Ground 3: Obviousness over NEC-Databook, TI-Datasheet, and Kikinis - Claims 4 and 5 are obvious over NEC-Databook in view of the TI-TPS5210-Datasheet, further in view of Kikinis.

  • Prior Art Relied Upon: NEC-Databook, TI-TPS5210-Datasheet (a 1999 regulator controller datasheet), and Kikinis (Patent 5,919,262).
  • Core Argument for this Ground:
    • Prior Art Mapping: This ground addressed claim 4, which requires "furnishing an input to reduce an output voltage" and "providing a feedback signal to the voltage regulator." Petitioner argued the TI-Datasheet disclosed a synchronous-buck regulator (TPS5210) whose output voltage could be programmed by furnishing digital inputs (VID0-VID4) and was regulated via an external resistor-divider feedback signal (VSENSE). Kikinis taught a similar regulator but disclosed replacing one of the fixed feedback resistors with a dynamically adjustable, electronically controlled R-ladder. The R-ladder's resistance could be changed based on whether the processor was entering or leaving a sleep state, thereby dynamically adjusting the feedback signal to raise or lower the regulator's output voltage. For claim 5, this combination taught that the reduced output voltage depends on the prior output voltage, as both voltages are calculated as a multiple of the same reference voltage (VREF), with the multiple being determined by the state of the adjustable R-ladder.
    • Motivation to Combine: A POSITA would have been motivated to combine these references to create a dynamically adjustable power supply for the NEC-Databook processor. The TI-Datasheet provided a suitable programmable regulator, and Kikinis provided a known, complementary technique for dynamically adjusting its feedback loop to enable efficient transitions between operating and sleep states. This combination represented a well-understood design pattern for implementing dynamic voltage scaling to achieve predictable power savings.

4. Arguments Regarding Discretionary Denial

  • Petitioner argued that discretionary denial under Fintiv was inappropriate. Key arguments included:
    • The trial date in the parallel district court litigation was likely to slip, increasing the probability that the Board’s Final Written Decision (FWD) would issue first.
    • Investment in the district court case was not yet significant, as no substantive rulings had been made and claim construction briefing was not yet complete.
    • The petition presented strong grounds for invalidity, a factor that weighs in favor of institution.

5. Relief Requested

  • Petitioner requested institution of an inter partes review and cancellation of claims 1-7 of the ’731 patent as unpatentable under 35 U.S.C. §103.