PTAB
IPR2021-01421
Microchip Technology Inc v. HD Silicon Solutions LLC
Key Events
Petition
Table of Contents
petition
1. Case Identification
- Case #: IPR2021-01421
- Patent #: 7,260,731
- Filed: September 14, 2021
- Petitioner(s): Microchip Technology, Inc.
- Patent Owner(s): HD Silicon Solutions LLC
- Challenged Claims: 8-18
2. Patent Overview
- Title: Saving Power When in or Transitioning to a Static Mode of a Processor
- Brief Description: The ’731 patent discloses methods and circuits for reducing a processor's static power consumption when its clock is disabled (i.e., in a "deep sleep" or static mode). The invention reduces the core voltage supplied to the processor to a level sufficient to maintain its state but insufficient for computation, allowing for quick resumption of operations when the clock is re-enabled.
3. Grounds for Unpatentability
Ground 1: Obviousness over Helms, Maxim-165X-Datasheet, and MAX1711-Kit - Claims 8-11 and 14 are obvious over Helms in view of Maxim-165X-Datasheet and MAX1711-Kit.
- Prior Art Relied Upon: Helms (Patent 6,748,545), Maxim-165X-Datasheet (a July 1998 datasheet), and MAX1711-Kit (a November 1999 evaluation kit document).
- Core Argument for this Ground:
- Prior Art Mapping: Petitioner argued that Helms taught the core of independent claim 8: a circuit with a voltage regulator (DC/DC converter) that supplies a processor with a selectable voltage. Helms’s regulator uses a multiplexer to select between an operating voltage (OVID) for computing mode and a lower sleep voltage (SVID) for sleep mode, which is sufficient to maintain the processor's state. To meet the limitations of claim 8[c] regarding power saving during a voltage transition, Petitioner turned to the Maxim-165X-Datasheet and MAX1711-Kit. These references taught that voltage regulators commonly operate in a pulse-width modulation (PWM) mode (continuous, low-noise) or a pulse-frequency modulation (PFM) mode (discontinuous, high-efficiency at light loads). They further taught that during a high-to-low voltage transition, operating in PFM mode dissipates excess charge through the load, wasting power. By forcing the regulator into PWM mode during the transition (via a dedicated input pin), the regulator could sink current, allowing excess charge to be conserved (e.g., returned to an input capacitor or battery) instead of dissipated. This combination allegedly met all limitations of claim 8. Dependent claims 9-11 and 14 were allegedly met by further details in the same references.
- Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine these references to improve the overall power efficiency of the system taught by Helms. While Helms focused on saving processor power by lowering voltage, a POSITA would recognize that the voltage regulator itself consumes power. The Maxim-165X-Datasheet and MAX1711-Kit taught a known, well-understood technique for improving regulator efficiency during voltage transitions. Applying this known power-saving technique to the voltage regulator in Helms’s known system would have been an obvious path to a more efficient design with predictable results. Furthermore, Helms explicitly contemplated using a MAX1711 regulator, making the combination particularly straightforward.
- Expectation of Success: A POSITA would have had a high expectation of success, as the combination involved applying a standard power-saving feature (forcing PWM mode) from one commercial regulator datasheet to a system designed to use such regulators.
Ground 2: Obviousness over Helms, TI-TPS5210-Datasheet, and Nilsson - Claims 12, 13, and 15-18 are obvious over Helms in view of TI-TPS5210-Datasheet and Nilsson.
- Prior Art Relied Upon: Helms (Patent 6,748,545), TI-TPS5210-Datasheet (a May 1999 datasheet), and Nilsson (a 1993 textbook on electronic circuits).
- Core Argument for this Ground:
- Prior Art Mapping: This ground addressed claims requiring means for reducing the selectable voltage below a lowest level the voltage regulator is specified to output. Petitioner again used Helms to teach the base system of selecting between operating and sleep voltages. The TI-TPS5210-Datasheet disclosed a voltage regulator with a standard resistor-voltage-divider feedback circuit, which allowed for adjusting the output voltage but only by raising it relative to a reference voltage (VREF). Petitioner argued that Nilsson, a textbook, taught a fundamental, well-known modification to this type of feedback circuit. By connecting a second, external voltage source to the lower leg of the voltage divider (instead of connecting it to ground), the operational amplifier's output could be adjusted both up and down relative to the reference voltage. By applying this textbook modification to the TI regulator and setting the external voltage source higher than the regulator's reference voltage, the regulator's output could be forced below its lowest specified level, thereby meeting the key limitation of independent claims 12 and 13.
- Motivation to Combine: A POSITA would have been motivated to use the TI-TPS5210 regulator in Helms's system, as it was an equivalent to the MAX1711 regulator suggested by Helms. A POSITA would further be motivated to modify the TI regulator's feedback circuit according to the textbook teachings of Nilsson to achieve greater flexibility and finer control over the output voltage. While the TI-TPS5210-Datasheet only taught raising the output voltage, the modification from Nilsson provided the predictable and desirable ability to also lower the voltage, including below the standard VREF, which would be useful for creating very low-power sleep states.
- Expectation of Success: The combination involved applying a standard, textbook circuit configuration (from Nilsson) to a standard commercial regulator (TI-TPS5210) to enhance its functionality in a predictable way. A POSITA would have had a clear expectation that this straightforward modification would work as expected.
4. Arguments Regarding Discretionary Denial
- Petitioner argued that discretionary denial under Fintiv would be inappropriate. The petition asserted that the scheduled trial date in the parallel district court litigation was likely to be delayed past the statutory deadline for the IPR's Final Written Decision, particularly given a pending motion to transfer venue. Petitioner also contended that investment in the district court proceeding had been minimal, with no substantive rulings issued and claim construction briefing still underway. Finally, Petitioner argued that the strength of its invalidity grounds weighed heavily in favor of institution.
5. Relief Requested
- Petitioner requested institution of an inter partes review and cancellation of claims 8-18 of the ’731 patent as unpatentable.
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