PTAB

IPR2021-01556

NXP USA Inc v. Impinj Inc

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Petition
petition

1. Case Identification

2. Patent Overview

  • Title: RFID Integrated Circuit Identifier Self-Check
  • Brief Description: The ’198 patent describes a Radio Frequency Identification (RFID) integrated circuit (IC) containing a memory and a processing block. The memory stores an identifier and an associated check code, and the processing block is configured to retrieve both, check the identifier for corruption, and, in some instances, reconstruct a correct identifier or indicate that an error has occurred.

3. Grounds for Unpatentability

Ground 1: Obviousness over Oga, Gen2, and Li - Claims 1-20 are obvious over Oga in view of Gen2, and further in view of Li.

  • Prior Art Relied Upon: Oga (Japanese Application # 2006-72426), Gen2 (EPC RFID Protocol Standard), and Li (US Application # 2008/0307270).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Oga disclosed the core features of an RFID IC capable of self-correction. Oga’s tag included a memory storing data (an identifier) and corresponding "error detection/correction codes" (a check code). It further taught a processing block ("error detecting and correcting unit") that retrieves the data, checks for errors, corrects them if possible to reconstruct a correct identifier, and outputs signals indicating whether the error was correctable or uncorrectable. For claims requiring a response with a corrupted identifier (claims 8-14, 15, 20), Petitioner argued Li taught returning data from a memory device even if error correction fails, as portions of the data may still be usable.
    • Motivation to Combine: A Person of Ordinary Skill in the Art (POSITA) would combine Oga with Gen2 because Gen2 was the prevailing industry standard for passive RFID tags. This combination would ensure interoperability and provide standardized protocols for memory architecture and packetized data transmission, which Oga did not fully detail. Specifically, a POSITA would use Gen2’s teachings to store error codes in memory before transmission to improve communication reliability. A POSITA would further combine Li’s teaching to gain the benefit of recovering partially useful data from an otherwise uncorrectable identifier, a known issue in RFID applications like inventory management where parts of an Electronic Product Code (EPC) remain valuable despite minor corruption.
    • Expectation of Success: Petitioner asserted a POSITA would have a high expectation of success, as the combination involved implementing a known error-correction scheme (Oga) within the framework of a well-defined industry standard (Gen2) and adding a known data-recovery strategy (Li).

Ground 2: Obviousness over Hasegawa and Gen2 - Claims 1-7 are obvious over Hasegawa in view of Gen2.

  • Prior Art Relied Upon: Hasegawa (Japanese Application # 2008-250426) and Gen2 (EPC RFID Protocol Standard).
  • Core Argument for this Ground:
    • Prior Art Mapping: As an alternative primary reference, Petitioner contended Hasegawa taught an RFID tag with on-tag error detection and correction. Hasegawa disclosed a memory storing user data alongside corresponding Cyclic Redundancy Check (CRC) and Error Correction Code (ECC) check codes. Its control circuit retrieves the data, performs a CRC check, and, if an error is found, performs 1-bit error correction using the ECC data to reconstruct the correct identifier.
    • Motivation to Combine: The motivation was parallel to that for combining Oga and Gen2. A POSITA would combine Hasegawa's specific error correction techniques with the ubiquitous Gen2 standard to increase the tag’s compatibility, adoption, and to utilize Gen2's standardized protocols for communication and memory organization. This would involve storing Hasegawa’s generated error notifications in memory as taught by Gen2 before transmission as a data packet.
    • Expectation of Success: Integrating Hasegawa's disclosed error correction logic with the standard Gen2 protocol was a predictable design choice for a POSITA seeking to create a commercially viable RFID tag.

Ground 3: Obviousness over Shimura, Hasegawa, and Gen2 - Claims 8-20 are obvious over Shimura in view of Hasegawa and Gen2.

  • Prior Art Relied Upon: Shimura (US Application # 2012/0068831), Hasegawa (Japanese Application # 2008-250426), and Gen2 (EPC RFID Protocol Standard).
  • Core Argument for this Ground:
    • Prior Art Mapping: Petitioner argued that Shimura taught an inefficient error detection method using "mirrored" data, where two copies of an identifier are stored and compared. If the copies did not match, the read operation failed and terminated, even if one of the two copies was correct.
    • Motivation to Combine: A POSITA would have been motivated to improve Shimura's inefficient system by incorporating Hasegawa's on-tag error detection and correction logic. Applying Hasegawa's CRC/ECC checks to each of Shimura's mirrored data copies would allow the tag to identify which copy was correct or even repair a 1-bit error, thus converting a failed read in Shimura into a successful one. Furthermore, Hasegawa’s "error correction notification" would allow a system operator to proactively identify and replace deteriorating tags, a significant improvement over Shimura's system. Gen2 would provide the standard framework for implementing these combined functionalities.
    • Expectation of Success: Combining these known error-handling techniques (mirroring from Shimura and ECC from Hasegawa) to create a more robust and efficient system represented a straightforward design path for a POSITA with a reasonable expectation of success.

4. Relief Requested

  • Petitioner requests institution of an inter partes review and cancellation of claims 1-20 of the ’198 patent as unpatentable.